Semiconductor device having stacked chips

Patent metadata

Field	Value
Publication number	US-8928399-B2
Application number	US-201313843165-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Sep 6, 2012
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.

First claim

What is claimed is:

1. A semiconductor device comprising:
chips each of which has at least first and second vias through each chip from a front surface of the chip to a back surface of the chip, the vias enabling transmission of at least first and second address signals, and the chips being electrically connected to each other through the first and second vias; and
a first selection circuit which is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of performing an arithmetic operation of the first and second address signals to a subsequent chip;
wherein the first selection circuit comprises:
an inversion circuit that is provided in each chip, inverts the first address signal, and supplies the inverted first address signal to a subsequent chip through the first via; and
a first logical operation circuit which is provided in each chip, performs a logical operation of the second address signal and the inverted first address signal, and supplies an arithmetic operation output signal to a subsequent chip through the second via provided in each chip.

2. The device according to claim 1 , wherein the first selection circuit further comprises:
a third via that allows transmission of a third address signal;
a fourth via that allows transmission of a fourth address signal;
a second logical operation circuit which performs a logical operation of the arithmetic operation output signal from the first logical operation circuit and the third address, and supplies an arithmetic operation output signal to a subsequent chip through the third via provided in each chip; and
a third logical operation circuit which performs a logical operation of the arithmetic operation output signal from the second logical operation circuit and the fourth address, and supplies an arithmetic operation output signal to a subsequent chip through the fourth via provided in each chip.

3. A solid-state drive (SSD) controller having a semiconductor device arranged thereon, the SSD controller being connected to the semiconductor device through an interface chip arranged between the SSD controller and the semiconductor device, and the semiconductor device comprising:
chips each of which has at least first and second vias through each chip from a front surface of the chip to a back surface of the chip, the vias enabling transmission of at least first and second address signals, and the chips being electrically connected to each other through the first and second vias; and
a first selection circuit which is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of performing an arithmetic operation of the first and second address signals to a subsequent chip.

4. A semiconductor device comprising:
chips each of which has at least first and second vias through each chip from a front surface of the chip to a back surface of the chip, the vias enabling transmission of at least first and second address signals, and the chips being electrically connected to each other through the first and second vias; and
a first selection circuit which is provided in each chip, includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of performing an arithmetic operation of the first and second address signals to a subsequent chip;
wherein each chip comprises:
memory cell arrays; and
peripheral circuits which are provided between the memory cell arrays; and
wherein the vias are arranged between the peripheral circuits.

Assignees

• Toshiba Kk

Inventors

• Koyanagi Masaru

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/879

  Bump connectors and bond wires · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/859

  Bump connectors and bond wires · CPC title