Digital phase-locked loop and related merged duty cycle calibration scheme for frequency synthesizers
US-2024171181-A1 · May 23, 2024 · US
US8928384B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928384-B2 |
| Application number | US-201314018034-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 4, 2013 |
| Priority date | Jun 10, 2011 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase.
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What is claimed is: 1. A cascaded interpolator, comprising: a plurality of single-bit interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate therefrom two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals, each of said single-bit interpolator stages comprising a 2:1 multiplexer and a 1:1 interpolator; and a phase con…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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