Integrated Assemblies Having Conductive Posts Extending Through Stacks of Alternating Materials
US-2024237336-A9 · Jul 11, 2024 · US
3D non-volatile memory device, memory system including the same, and method of manufacturing the same
US8928144B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928144-B2 |
| Application number | US-201213599956-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 30, 2012 |
| Priority date | Dec 20, 2011 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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A three-dimensional 3D nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal patterns; and a diffusion barrier layer interposed between the barrier metal patterns and the charge blocking layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A 3-Dimensional (3D) non-volatile memory device comprising: vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; barrier metal patterns surrounding the conductive layer patterns, respectively, wherein the barrier metal patterns include first impurities; a charge blocking layer interposed between the vertical channel layers and the barrier…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/0413Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8928144B2 cover?
- A three-dimensional 3D nonvolatile memory device includes vertical channel layers protruding from a substrate; interlayer insulating layers and conductive layer patterns alternately deposited along the vertical channel layers; a barrier metal pattern surrounding each of the conductive layer patterns; a charge blocking layer interposed between the vertical channel layers and the barrier metal pa…
- Who is the assignee on this patent?
- Kim Suk Goo, Sk Hynix Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0413. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).