Semiconductor package having internal shunt and solder stop dimples

Patent metadata

Field	Value
Publication number	US-8928115-B2
Application number	US-201313757640-A
Country	US
Kind code	B2
Filing date	Feb 1, 2013
Priority date	Dec 21, 2005
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction.

First claim

What is claimed is:

1. A semiconductor package comprising:
first and second conductive layers on top and bottom surfaces of an insulation layer;
a semiconductor die mounted on said first conductive layer and having an electrode electrically connected to said first conductive layer;
a current sense resistor situated in an opening extending from said top surface to said bottom surface of said insulation layer, said current sense resistor electrically connected to said first and…

Assignees

• Int Rectifier Corp

Inventors

• Hauenstein Henning M

Classifications

• H10W74/00

  Electricity · mapped topic

• H10W72/0198

  Electricity · mapped topic

• H10W72/075

  Electricity · mapped topic

• H10W72/884

  Electricity · mapped topic

• H10W90/754

  Electricity · mapped topic