Buried-channel field-effect transistors

Patent metadata

Field	Value
Publication number	US-8928096-B2
Application number	US-201213474949-A
Country	US
Kind code	B2
Filing date	May 18, 2012
Priority date	May 14, 2012
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

A buried-channel field-effect transistor includes a semiconductor layer formed on a substrate. The semiconductor layer includes doped source and drain regions and an undoped channel region. the transistor further includes a gate dielectric formed over the channel region and partially overlapping the source and drain regions; a gate formed over the gate dielectric; and a doped shielding layer between the gate dielectric and the semiconductor layer.

First claim

What is claimed is:

1. A buried-channel field-effect transistor (FET) comprising:
a semiconductor layer formed on a substrate comprising:
doped source and drain regions; and
an undoped channel region;

a gate dielectric formed over the channel region and partially overlapping the source and drain regions, wherein the gate dielectric consists of a single dielectric material;
a gate formed over the gate dielectric, such that the gate dielectric has a ‘u’-shaped cross-section…

Assignees

• Cheng Kangguo
• Khakifirooz Ali
• Kulkarni Pranita
• Ning Tak H
• IBM

Inventors

• Cheng Kangguo
• Khakifirooz Ali
• Kulkarni Pranita
• Ning Tak H

Classifications

• H10D84/0167

  Electricity · mapped topic

• H10D84/038

  Electricity · mapped topic

• H10D64/691

  Electricity · mapped topic

• H10D30/60

  Electricity · mapped topic

• H10D86/201 Primary

  Electricity · mapped topic