Semiconductor device
US-2024421048-A1 · Dec 19, 2024 · US
Semiconductor devices and methods of fabricating the same
US8928092B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928092-B2 |
| Application number | US-201313940721-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 12, 2013 |
| Priority date | Jul 12, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and a diffusion barrier pattern in contact with the portion of the top surface of the lower gate pattern and extending between the residual insulating pattern and the upper gate pattern.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a lower insulating pattern on a semiconductor substrate; a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer; a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern; an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening; and a diffusion barrier pattern in contact with the port…
Assignees
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Classifications
- H10W72/00Primary
Electricity · mapped topic
- H10D30/681Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8928092B2 cover?
- A semiconductor device includes a lower insulating pattern on a semiconductor substrate, a lower gate pattern on the lower insulating pattern and formed of a doped polysilicon layer, a residual insulating pattern with an opening exposing a portion of a top surface of the lower gate pattern, an upper gate pattern on the residual insulating pattern, the upper gate pattern filling the opening, and…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W72/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).