Display Substrate, Display Substrate Motherboard and Display Apparatus
US-2024355831-A1 · Oct 24, 2024 · US
US8928085B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928085-B2 |
| Application number | US-201313852883-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 28, 2013 |
| Priority date | Jun 9, 2010 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Official abstract text for this publication.
Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: a substrate; a first p-well in the substrate, wherein the first p-well is configured to operate as a base of a first NPN bipolar transistor; a first p-type base contact region in the first p-well; an n-type isolation structure configured to electrically isolate the first p-well from the substrate, and wherein the n-type isolation structure is electrically connected to a first node; a first n-type emitter region in the first p…
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