JLT (junction-less transistor) device and method for fabricating the same

US8928082B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8928082-B2
Application numberUS-201313921209-A
CountryUS
Kind codeB2
Filing dateJun 19, 2013
Priority dateFeb 26, 2013
Publication dateJan 6, 2015
Grant dateJan 6, 2015

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Abstract

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A method for fabricating a junction-less transistor device that includes a substrate, a buried dielectric layer having a fin structure on the substrate, a doped region formed through the buried dielectric layer in the substrate, a semiconductor layer overlying the buried dielectric layer and the doped region, a gate structure on the semiconductor layer, and source/drain regions in the semiconductor layer at opposite sides of the gate structure. The semiconductor layer includes first, second, third regions, with the second region interposed between the first and second regions and disposed underneath the gate electrode structure. The first, second, and third regions have a same doping polarity. The second region has a doping concentration less than those of the first and second regions. The second region and the doped region have opposite doping polarities. The second region has a groove in contact with a bottom portion of the gate structure.

First claim

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What is claimed is: 1. A junction less-transistor comprising: a substrate; a buried dielectric layer having a fin structure on the substrate; a doped region formed through the buried dielectric layer and in the substrate; a semiconductor material layer overlying the buried dielectric layer and the doped region; a gate structure wrapping around a portion of the semiconductor material layer; and source/drain structures formed in the semiconductor material layer at opposite…

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What does patent US8928082B2 cover?
A method for fabricating a junction-less transistor device that includes a substrate, a buried dielectric layer having a fin structure on the substrate, a doped region formed through the buried dielectric layer in the substrate, a semiconductor layer overlying the buried dielectric layer and the doped region, a gate structure on the semiconductor layer, and source/drain regions in the semicondu…
Who is the assignee on this patent?
Semiconductor Mfg Int Shanghai
What technology area does this patent fall under?
Primary CPC classification H10D64/519. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).