Semiconductor device structure with work function layer and method for forming the same
US-2024322009-A1 · Sep 26, 2024 · US
US8928082B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928082-B2 |
| Application number | US-201313921209-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 19, 2013 |
| Priority date | Feb 26, 2013 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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A method for fabricating a junction-less transistor device that includes a substrate, a buried dielectric layer having a fin structure on the substrate, a doped region formed through the buried dielectric layer in the substrate, a semiconductor layer overlying the buried dielectric layer and the doped region, a gate structure on the semiconductor layer, and source/drain regions in the semiconductor layer at opposite sides of the gate structure. The semiconductor layer includes first, second, third regions, with the second region interposed between the first and second regions and disposed underneath the gate electrode structure. The first, second, and third regions have a same doping polarity. The second region has a doping concentration less than those of the first and second regions. The second region and the doped region have opposite doping polarities. The second region has a groove in contact with a bottom portion of the gate structure.
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What is claimed is: 1. A junction less-transistor comprising: a substrate; a buried dielectric layer having a fin structure on the substrate; a doped region formed through the buried dielectric layer and in the substrate; a semiconductor material layer overlying the buried dielectric layer and the doped region; a gate structure wrapping around a portion of the semiconductor material layer; and source/drain structures formed in the semiconductor material layer at opposite…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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