Vertical JFET with body diode and device regions disposed in a single compound epitaxial layer
US-9209318-B2 · Dec 8, 2015 · US
Vertical junction field effect transistors and diodes having graded doped regions and methods of making
US8928074B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928074-B2 |
| Application number | US-201213434976-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 30, 2012 |
| Priority date | Jun 19, 2009 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
First claim
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What is claimed is: 1. A vertical junction field effect transistor (JFET) semiconductor device comprising: an n-type semiconductor substrate electrically coupled to a drain electrode of the JFET semiconductor device; a layer of n-type semiconductor material above the substrate; one or more gate regions of p-type semiconductor material on the layer of n-type semiconductor material, each of the one or more gate regions having a graded dopant concentration and being electrically…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8928074B2 cover?
- Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semicondu…
- Who is the assignee on this patent?
- Cheng Lin, Mazzola Michael, Power Integrations Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D30/831. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).