Gate isolation features and methods of fabricating the same in semiconductor devices
US-2024379673-A1 · Nov 14, 2024 · US
Semiconductor devices including guard ring structures
US8928073B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928073-B2 |
| Application number | US-201313787147-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 6, 2013 |
| Priority date | Mar 20, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a substrate including a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region; a guard ring formed in the interface region of the substrate and surrounding the cell region, wherein the guard ring comprises a portion of the substrate at an upper surface of the substrate and is defined by two adjacent isolation layers at the upper surface of the substrate…
Assignees
Inventors
Classifications
Electricity · mapped topic
- H10D84/0151Primary
Electricity · mapped topic
Electricity · mapped topic
- H10D84/0142Primary
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8928073B2 cover?
- A semiconductor device includes a substrate partitioned into a cell region, a peripheral circuit region, and an interface region between the cell region and the peripheral circuit region. A guard ring is provided in the interface region of the substrate and surrounds the cell region. A first gate structure is in the cell region, and a second gate structure is in the peripheral circuit region.
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D84/0151. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).