Gate stack of boron semiconductor alloy, polysilicon and high-K gate dielectric for low voltage applications

Patent metadata

Field	Value
Publication number	US-8928064-B2
Application number	US-201314030520-A
Country	US
Kind code	B2
Filing date	Sep 18, 2013
Priority date	Mar 14, 2013
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate including a channel region, a source region and a drain region, wherein the source region and the drain region are on opposing sides of the channel region; and a gate structure present on the channel region of the semiconductor substrate, wherein the gate structure includes an interfacial oxide containing layer that is in direct contact with the channel region, a high-k gate dielectric layer that i…

Assignees

• IBM

Inventors

• Frank Martin M
• Lauer Isaac
• Sleight Jeffrey W

Classifications

• H10D64/01314

  Electricity · mapped topic

• H10D64/01308

  Electricity · mapped topic

• H10D64/691

  Electricity · mapped topic

• H10D64/662

  Electricity · mapped topic

• H10D64/514

  Electricity · mapped topic