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Non-volatile memory device and method for fabricating the same
US8928063B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928063-B2 |
| Application number | US-201213618182-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 14, 2012 |
| Priority date | Dec 22, 2011 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.
First claim
Opening claim text (preview).
What is claimed is: 1. A non-volatile memory device, comprising: a channel layer vertically extending from a substrate; a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer; and a memory layer interposed between the channel layer and each gate electrode, wherein the memory layer includes a charge storage laver, a tunnel insulation layer interposed between the charge storage layer and the channel…
Assignees
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Classifications
- H10D30/69Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D64/037Primary
Electricity · mapped topic
- H10B43/27Primary
Electricity · mapped topic
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- What does patent US8928063B2 cover?
- A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristi…
- Who is the assignee on this patent?
- Kim Min-Soo, Sheen Dong-Sun, Pyi Seung-Ho, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/69. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).