Semiconductor structure with reduced leakage current and method for manufacturing the same
US-2024413223-A1 · Dec 12, 2024 · US
MOSFET with source side only stress
US8928047B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928047-B2 |
| Application number | US-201113288170-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 3, 2011 |
| Priority date | Nov 3, 2010 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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Abstract
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An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.
First claim
Opening claim text (preview).
What is claimed is: 1. An integrated circuit having a drain extended metal oxide semiconductor (DeMOS) transistor, comprising: a semiconductor substrate; a gate over said semiconductor substrate; a channel in said semiconductor substrate beneath said gate; a source in said semiconductor substrate adjacent said channel, said source comprising a stress enhancement region comprising an implanted stress enhancing species which is not a dopant species; and a drain comprising a…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D30/797Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8928047B2 cover?
- An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by form…
- Who is the assignee on this patent?
- Nawaz Samuel Zafar, Yu Shaofeng, Brighton Jeffrey E, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification H10D30/797. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).