Multi-stack nanosheet structure including semiconductor device
US-2024023326-A1 · Jan 18, 2024 · US
Semiconductor device
US8928045B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928045-B2 |
| Application number | US-201213690995-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 30, 2012 |
| Priority date | Jun 7, 2010 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction. Second semiconductor regions each having a high impurity concentration and the second conductivity type are disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a channel region disposed in a surface portion of a semiconductor substrate and having a first conductivity type; a first semiconductor region disposed under the channel region in the semiconductor substrate and having a second conductivity type; a gate region disposed in a surface portion of the channel region and having the second conductivity type; and source/drain regions disposed in parts of the surface portion o…
Assignees
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Classifications
- H10D84/401Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8928045B2 cover?
- A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts…
- Who is the assignee on this patent?
- Panasonic Corp, Panasonic Ip Man Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D84/401. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).