Heterostructure power transistor with AlSiN passivation layer

Patent metadata

Field	Value
Publication number	US-8928037-B2
Application number	US-201313780192-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Feb 28, 2013
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.

First claim

We claim:

1. A heterostructure power transistor comprising:
a first active layer,
a second active layer disposed on the first active layer, a two-dimensional electron gas layer forming between the first and second active layers;
a passivation/gate dielectric layer comprising aluminum silicon nitride (AlSiN) disposed on the second active layer;
an AlN layer disposed above the passivation/gate dielectric layer;
a gate;
a second gate dielectric layer disposed on the AlN lay…

Assignees

• Power Integrations Inc

Inventors

• Ramdani Jamal
• Murphy Michael
• Edwards John Paul

Classifications

• H10P14/69433

  Electricity · mapped topic

• H10P14/69391

  Electricity · mapped topic

• H10P14/3416

  Electricity · mapped topic

• H10P14/60

  Electricity · mapped topic

• H10D62/8503

  Electricity · mapped topic