Semiconductor device and method for forming the same
US-2024395669-A1 · Nov 28, 2024 · US
Conductive via hole and method for forming conductive via hole
US8927433B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8927433-B2 |
| Application number | US-96946910-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 15, 2010 |
| Priority date | Dec 18, 2009 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reduction and precipitation of silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide series, which is generated during the flowing, on an upper layer inside of the via hole structure filled with silver.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for forming a conductive via hole, the method comprising: filling inside of a via hole structure that is formed in an upper portion of a substrate with silver by using a reduction and a precipitation of the silver in order to connect a plurality of stacked substrates by a conductor; filling a portion that is not filled with silver inside of the via hole structure by flowing silver thereinto; and sublimating residual material of silver oxide seri…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/023Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8927433B2 cover?
- Provided is a technology for forming a conductive via hole to implement a three dimensional stacked structure of an integrated circuit. A method for forming a conductive via hole according to an embodiment of the present invention comprises: filling inside of a via hole structure that is formed in one or more of an upper portion and a lower portion of a substrate with silver by using a reductio…
- Who is the assignee on this patent?
- Kang Jin-Yeong, Korea Electronics Telecomm
- What technology area does this patent fall under?
- Primary CPC classification H10W20/023. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).