Multi-stack nanosheet structure including semiconductor device
US-2024023326-A1 · Jan 18, 2024 · US
US8927367B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8927367-B2 |
| Application number | US-201313736457-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 8, 2013 |
| Priority date | Feb 27, 2012 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
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A method of fabricating a semiconductor device may include patterning a substrate to form trenches, forming a sacrificial layer to cover inner surfaces of the trenches, the sacrificial layer having a single-layered structure, forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches, forming lightly doped regions in sidewalls of the trenches using the sacrificial patterns as an ion mask, removing the sacrificial patterns, and sequentially forming a gate insulating layer and a gate electrode layer in the trenches.
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What is claimed is: 1. A method of fabricating a semiconductor device, comprising: patterning a substrate to form trenches; forming a sacrificial layer to cover inner surfaces of the trenches, the sacrificial layer having a single-layered structure; forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches; forming lightly doped regions in sidewalls of the trenches using the sacrific…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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