Dynamic offset calibration circuit and method for operating the same

Patent metadata

Field	Value
Publication number	US-2026100701-A1
Application number	US-202418910056-A
Country	US
Kind code	A1
Filing date	Oct 9, 2024
Priority date	Oct 9, 2024
Publication date	Apr 9, 2026
Grant date	—

Abstract

The present disclosure provides an integrated circuit which includes a first corrector circuit and a second corrector circuit. The first corrector circuit calibrates a first duty cycle of a first clock signal based on an offset calibration code to generate a first output clock signal. The second corrector circuit calibrate a second duty cycle of a second clock signal based on the offset calibration code to generate a second output clock signal. A first trim code includes a first upper portion and a first lower portion, and a second trim code includes a second upper portion and a second lower portion. A first portion of the offset calibration code is an average of the first upper portion and the second upper portion, and a second portion of the offset calibration code is an average of the first lower portion and the second lower portion.

First claim

1 . An integrated circuit, comprising:
a first corrector circuit, configured to receive a first clock signal and calibrate a first duty cycle of the first clock signal based on an offset calibration code to generate a first output clock signal; and a second corrector circuit, configured to receive a second clock signal and calibrate a second duty cycle of the second clock signal based on the offset calibration code to generate a second output clock signal, wherein the offset calibration code is obtained based on a first trim code associated with the first output clock signal and a second trim code associated with the second output clock signal, wherein the first trim code comprises a first upper portion and a first lower portion, and the second trim code comprises a second upper portion and a second lower portion, wherein a first portion of the offset calibration code is an average of the first upper portion and the second upper portion, and a second portion of the offset calibration code is an average of the first lower portion and the second lower portion.

2 . The integrated circuit of claim 1 , wherein the first clock signal is an in-phase clock signal, and the second clock signal is a quadrature phase clock signal having a 90 degree phase difference with respect to the first clock signal.

3 . The integrated circuit of claim 1 , further comprising:
a duty cycle corrector, configured to convert the first duty cycle of the first output clock signal and the second duty cycle of the second output clock signal to a first voltage signal and a second voltage signal, respectively; a chopper, configured to bypass the first voltage signal and the second voltage signal as a first chopped voltage signal and a second chopped voltage signal in a bypass mode; a first low-pass filter, configured to filter the first chopped voltage signal to generate a first signal; a second low-pass filter, configured to filter the second chopped voltage signal to generate a second signal; a comparator, configured to generate a comparison result of the first signal with respect to the second signal; and a finite state machine, configured to change an operating state in response to the comparison result and generate a trim code corresponding to the operating state.

4 . The integrated circuit of claim 3 , wherein the chopper is configured to swap the first voltage signal and the second voltage signal to generate the first chopped voltage signal and the second chopped voltage signal in a swap mode.

5 . The integrated circuit of claim 4 , wherein in response to the comparison result being in a low logic state, the finite state machine increases the trim code by 1, and feeds the trim code back to the first corrector circuit until the comparison result is flipped from the low logic state to a high logic state.

6 . The integrated circuit of claim 5 , wherein in response to the comparison result flipping from the low logic state to the high logic state, the finite state machine records the trim code currently used as the first trim code, and the chopper enters the swap mode to swap the first voltage signal and the second voltage signal to generate the first chopped voltage signal and the second chopped voltage signal.

7 . The integrated circuit of claim 6 , wherein in response to the comparison result being in the high logic state, the finite state machine decreases the trim code by 1, and feeds the trim code back to the second corrector circuit until the comparison result is flipped from the high logic state to the low logic state.

8 . The integrated circuit of claim 7 , wherein in response to the comparison result flipping from the high logic state to the low logic state, the finite state machine records the trim code currently used as the second trim code.

9 . The integrated circuit of claim 8 , wherein the finite state machine extracts the first upper portion and the first lower portion of the first trim code, and extracts the second upper portion and the second lower portion of the second trim code.

10 . The integrated circuit of claim 9 , wherein each bit of the first portion and the second portion of the offset calibration code constitute a first duty cycle difference and a second duty cycle difference of the first output clock signal, respectively, and the first duty cycle difference is relatively larger than the second duty cycle difference.

11 . The integrated circuit of claim 10 , wherein in response to the first portion of the offset calibration code being a fractional number with an integer part and a fractional part, an auxiliary bit associated with the fractional part is asserted to constitute half the first duty cycle difference of the first output clock signal.

12 . The integrated circuit of claim 11 , wherein the first correct circuit comprises:
a driving circuit, configured to receive the first clock signal to generate the first output clock signal; a first upper tuning circuit, comprising a plurality of first P-type transistors, each receiving a respective bit of an inversed first portion of the offset calibration code; a second upper tuning circuit, comprising a plurality of second P-type transistors, each receiving a respective bit of an inversed second portion of the offset calibration code; a first lower tuning circuit, comprising a plurality of first N-type transistors, each receiving a respective bit of the first portion of the offset calibration code; a second lower tuning circuit, comprising a plurality of second N-type transistors, each receiving a respective bit of the second portion of the offset calibration code; an upper auxiliary tuning circuit, comprising a plurality of third P-type transistors, each receiving a respective bit of an inversed auxiliary first trim code; and a lower auxiliary tuning circuit, comprising a plurality of third N-type transistors, each receiving a respective bit of an auxiliary first trim code.

13 . The integrated circuit of claim 12 , wherein:
a driving capability of the first P-type transistors and the third P-type transistors is relatively higher than that of the second P-type transistors; a driving capability of the first N-type transistors and the third N-type transistors is relatively higher than that of the second N-type transistors; and a driving capability of each of the P-type transistors and the third P-type transistors is substantially equal to that of each of the first N-type transistors and the third N-type transistors.

14 . The integrated circuit of claim 12 , wherein:
the driving circuit comprises a first inverter, a first driver, a second inverter, a third inverter, and a fourth inverter connected in series; the first upper tuning circuit is coupled between a power supply voltage and the second inverter; the second upper tuning circuit is coupled between the power supply voltage and the first driver; the first lower tuning circuit is coupled between a reference voltage and the second inverter; the second lower tuning circuit is coupled between the reference voltage and the first driver; the upper auxiliary tuning circuit is coupled between the power supply voltage and the second inverter; and the lower auxiliary tuning circuit is coupled between the reference voltage and the second inverter.

15 - 20 . (canceled)

21 . An integrated circuit, comprising:
a first corrector circuit, configured to receive an in-phase clock signal and calibrate a first duty cycle of the in-phase clock signal based on a first portion and a second portion of an offset calibration code to generate a first output clock signal; and a seco

Assignees

• Taiwan Semiconductor Mfg Company Ltd

Inventors

• Li Chang-Yi

Classifications

• H03K3/01

  Details · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title