Duty cycle correction circuit and method for operating the same

Patent metadata

Field	Value
Publication number	US-2026100700-A1
Application number	US-202418910043-A
Country	US
Kind code	A1
Filing date	Oct 9, 2024
Priority date	Oct 9, 2024
Publication date	Apr 9, 2026
Grant date	—

Abstract

The present disclosure provides an integrated circuit, which includes a master circuit and a slave circuit. The master circuit is configured to receive an input clock signal and generate an intermediate clock signal based on a first half and a second half of a first trimming code. The slave circuit is electrically connected to the master circuit and is configured to receive the intermediate clock signal and generate an output clock signal from the intermediate clock signal based on a first half and a second half of a second trimming code. The first trimming code is complementary to the second trimming code.

First claim

What is claimed is:

1 . An integrated circuit, comprising:
a master circuit, configured to receive an input clock signal and generate an intermediate clock signal based on a first half and a second half of a first trimming code; and a slave circuit, electrically connected to the master circuit, and configured to receive the intermediate clock signal and generate an output clock signal from the intermediate clock signal based on a first half and a second half of a second trimming code, wherein the first trimming code is complementary to the second trimming code.

2 . The integrated circuit of claim 1 , wherein the master circuit comprises:
a first trimming circuit, configured to receive the first half of the first trimming code to provide a first voltage; a second trimming circuit, configured to receive the second half of the first trimming code to provide a second voltage; and a master compensation circuit, configured to receive the input clock signal and generate the intermediate clock signal from the input clock signal based on the first voltage and the second voltage.

3 . The integrated circuit of claim 2 , wherein:
the first trimming circuit comprises a plurality of P-type transistors, each receiving a respective bit of the first half of the first trimming code; and the second trimming circuit comprises a plurality of N-type transistors, each receiving a respective bit of the second half of the first trimming code.

4 . The integrated circuit of claim 2 , wherein the master compensation circuit comprises:
a first inverter, configured to convert the input clock signal to generate a first clock signal at a first node; a first transistor, having a gate terminal receiving the intermediate clock signal, a first terminal receiving the first voltage, and a second terminal coupled to the first node; and a second transistor, having a gate terminal receiving the intermediate clock signal, a first terminal coupled to the first node, and a second terminal receiving the second voltage.

5 . The integrated circuit of claim 4 , wherein the master compensation circuit further comprises:
a first frequency calibration circuit, configured to receive a first frequency option signal to generate a third voltage; a second frequency calibration circuit, configured to receive a second frequency option signal complementary to the first frequency option signal to generate a fourth voltage; a third transistor, having a gate terminal receiving the first clock signal, a first terminal receiving the third voltage, and a second terminal coupled to a second node; and a fourth transistor, having a gate terminal receiving the first clock signal, a first terminal coupled to the second node, and a second terminal receiving the fourth voltage, wherein the master compensation circuit generates the intermediate clock signal at the second node.

6 . The integrated circuit of claim 5 , wherein:
the first frequency calibration circuit comprises a plurality of P-type transistors, each receiving a respective bit of the first frequency option signal; and the second frequency calibration circuit comprises a plurality of N-type transistor, each receiving a respective bit of the second frequency option signal.

7 . The integrated circuit of claim 5 , wherein the slave circuit comprises:
a third trimming circuit, configured to receive the second half of the second trimming code to provide a fifth voltage; a fourth trimming circuit, configured to receive the first half of the second trimming code to provide a sixth voltage; and a slave compensation circuit, configured to receive the intermediate clock signal at the second node and generate the output clock signal from the intermediate clock signal based on the fifth voltage and the sixth voltage.

8 . The integrated circuit of claim 7 , wherein:
the third trimming circuit comprises a plurality of P-type transistors, each receiving a respective bit of the second half of the second trimming code; and the fourth trimming circuit comprises a plurality of N-type transistors, each receiving a respective bit of the first half of the second trimming code.

9 . The integrated circuit of claim 7 , wherein the slave compensation circuit comprises:
a fifth transistor, having a gate terminal receiving a feedback clock signal, a first terminal receiving the fifth voltage, and a second terminal coupled to the second node; and a sixth transistor, having a gate terminal receiving the feedback clock signal, a first terminal coupled to the second node, and a second terminal receiving the sixth voltage.

10 . The integrated circuit of claim 9 , wherein the slave compensation circuit further comprises:
a third frequency calibration circuit, configured to receive the first frequency option signal to generate a seventh voltage; a fourth frequency calibration circuit, configured to receive the second frequency option signal to generate an eighth voltage; a seventh transistor, having a gate terminal receiving the intermediate clock signal, a first terminal receiving the seventh voltage, and a second terminal coupled to a third node; an eighth transistor, having a gate terminal receiving the intermediate clock signal, a first terminal coupled to the third node, and a second terminal receiving the eighth voltage; and a second inverter, configured to convert the feedback clock signal generated at the third node to generate the output clock signal.

11 . The integrated circuit of claim 1 , wherein the first half and the second half of the first trimming code refers to an upper half and a lower half of the first trimming code, respectively.

12 . The integrated circuit of claim 1 , wherein the first half and the second half of the first trimming code refers to a lower half and an upper half of the first trimming code, respectively.

13 . The integrated circuit of claim 1 , wherein the first half and the second half of the first trimming code refers to even-number indexed bits and odd-number indexed bits of the first trimming code, respectively.

14 . The integrated circuit of claim 5 , wherein:
the first trimming circuit receives a power supply voltage and is coupled to the first transistor; the second trimming circuit receives a reference voltage and is coupled to the second transistor; the first frequency calibration circuit receives the power supply voltage and is coupled to the third transistor; and the second frequency calibration circuit receives the reference voltage and is coupled to the fourth transistor.

15 . The integrated circuit of claim 5 , wherein:
the first trimming circuit receives a power supply voltage and is coupled to the master compensation circuit through the first frequency calibration circuit; and the second trimming circuit receives a reference voltage and is coupled to the master compensation circuit through the second frequency calibration circuit.

16 . An integrated circuit, comprising:
a master circuit, configured to receive an input clock signal and generate an intermediate clock signal based on a first trimming code; and a slave circuit, electrically connected to the master circuit, and configured to receive the intermediate clock signal and generate an output clock signal from the intermediate clock signal based on a second trimming code complementary to the first trimming code.

17 . The integrated circuit of claim 16 , wherein the master circuit comprises:
a first frequency calibration circuit, comprising a plurality of transmission gates, each receiving the intermediate clock signal and

Assignees

• Taiwan Semiconductor Mfg Company Ltd

Inventors

• Li Chang-Yi

Classifications

• H03K5/14

  by the use of delay lines (H03K5/133 takes precedence) · CPC title

• H03K5/131

  Digitally controlled · CPC title

• H03K2005/00058

  controlled by a digital setting · CPC title

• H03K3/0372

  of the primary-secondary type · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title