System state save and restore mechanism using hold latch cell

Patent metadata

Field	Value
Publication number	US-2026100697-A1
Application number	US-202418908656-A
Country	US
Kind code	A1
Filing date	Oct 7, 2024
Priority date	Oct 7, 2024
Publication date	Apr 9, 2026
Grant date	—

Abstract

Aspects of the disclosure are directed to a test mode save and restore operation. In accordance with one aspect, the disclosure includes a hold latch cell configured to execute a save directive for a first operational state of a digital logic system and to execute a restore directive for the first operational state in the digital logic system in an operational mode; a first multiplexer coupled to the hold latch cell, the first multiplexer configured to execute a test sequence on the digital logic system in a test mode; and a logical XOR circuit coupled to the hold latch cell, the logical XOR circuit configured to perform a fault detection on the save directive and the restore directive to generate an error flag signal.

First claim

What is claimed is:

1 . An apparatus comprising:
a hold latch cell configured to execute a save directive for a first operational state of a digital logic system and to execute a restore directive for the first operational state in the digital logic system in an operational mode; a first multiplexer coupled to the hold latch cell, the first multiplexer configured to execute a test sequence on the digital logic system in a test mode; and a logical XOR circuit coupled to the hold latch cell, the logical XOR circuit configured to perform a fault detection on the save directive and the restore directive to generate an error flag signal.

2 . The apparatus of claim 1 , further comprising a second multiplexer coupled to the first multiplexer, the second multiplexer configured to initialize the digital logic system in the operational mode with the first operational state.

3 . The apparatus of claim 2 , further comprising a flip flop circuit coupled to the second multiplexer, the flip flop circuit configured to transition from the first operational state to a second operational state using one or more updated inputs in the digital logic system in the operational mode.

4 . The apparatus of claim 3 , wherein the save directive and the restore directive are executed over a multi cycle path (MCP).

5 . The apparatus of claim 3 , wherein the save directive and the restore directive are executed with a clock signal disabled.

6 . An apparatus comprising:
means for executing a save directive for a first operational state of a digital logic system using a hold latch cell in an operational mode; means for executing a test sequence on the digital logic system in a test mode; means for executing a restore directive for the first operational state in the digital logic system in the operational mode; and means for performing a fault detection on the save directive and the restore directive to generate an error flag signal.

7 . The apparatus of claim 6 , further comprising:
means for initializing the digital logic system in the operational mode with the first operational state; and means for transitioning the digital logic system from the operational mode to the test mode.

8 . The apparatus of claim 7 , further comprising:
means for transitioning the digital logic system from the test mode to the operational mode; and means for transitioning from the first operational state to a second operational state using one or more updated inputs in the digital logic system in the operational mode.

9 . A method comprising:
executing a save directive for a first operational state of a digital logic system using a hold latch cell in an operational mode; executing a test sequence on the digital logic system in a test mode; executing a restore directive for the first operational state in the digital logic system in the operational mode; and performing a fault detection on the save directive and the restore directive to generate an error flag signal.

10 . The method of claim 9 , wherein the save directive saves the first operational state in a hold latch cell.

11 . The method of claim 10 , wherein the save directive utilizes a save signal to trigger a transition in a state output.

12 . The method of claim 11 , wherein the state output is an output state of the hold latch cell.

13 . The method of claim 9 , wherein the executing the restore directive is performed over a multi cycle path (MCP).

14 . The method of claim 13 , wherein the executing the restore directive is performed with a clock signal disabled.

15 . The method of claim 9 , wherein the executing the save directive is performed over a multi cycle path (MCP).

16 . The method of claim 15 , wherein the executing the save directive is performed with a clock signal disabled.

17 . The method of claim 9 , further comprising initializing the digital logic system in the operational mode with the first operational state.

18 . The method of claim 17 , further comprising transitioning the digital logic system from the operational mode to the test mode.

19 . The method of claim 18 , further comprising transitioning the digital logic system from the test mode to the operational mode.

20 . The method of claim 19 , further comprising transitioning from the first operational state to a second operational state using one or more updated inputs in the digital logic system in the operational mode.

Assignees

• Qualcomm Incorporated

Inventors

• Patil Srinivas
• Li Qing Yun
• Maor Nir

Classifications

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K17/002

  Switching arrangements with several input- or output terminals (code converters H03M5/00, H03M7/00) · CPC title

• G01R31/318525

  Test of flip-flops or latches · CPC title

• G01R31/3187

  Built-in tests · CPC title

• H03K3/037 Primary

  Bistable circuits · CPC title