Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2026096105-A1
Application number	US-202519226735-A
Country	US
Kind code	A1
Filing date	Jun 3, 2025
Priority date	Sep 27, 2024
Publication date	Apr 2, 2026
Grant date	—

Abstract

Provided is a semiconductor memory device including a substrate, an interlayer insulating layer on the substrate, lower contact plugs penetrating the interlayer insulating layer, magnetic tunnel junction patterns on the lower contact plugs, respectively, lower electrodes between the lower contact plugs and the magnetic tunnel junction patterns, respectively, a buffer insulating layer between the lower electrodes and on the interlayer insulating layer, a capping insulating layer on a sidewall of each of the magnetic tunnel junction patterns and an upper surface of the buffer insulating layer, and upper electrodes on the magnetic tunnel junction patterns, respectively.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a substrate; an interlayer insulating layer on the substrate; lower contact plugs penetrating the interlayer insulating layer; magnetic tunnel junction patterns on the lower contact plugs, respectively; lower electrodes between the lower contact plugs and the magnetic tunnel junction patterns, respectively; a buffer insulating layer between the lower electrodes and on the interlayer insulating layer; a capping insulating layer on a sidewall of each of the magnetic tunnel junction patterns and an upper surface of the buffer insulating layer; and upper electrodes on the magnetic tunnel junction patterns, respectively.

2 . The semiconductor memory device of claim 1 , wherein a lower surface of the capping insulating layer is at a level between an upper surface of each of the lower electrodes and a lower surface of each of the lower electrodes.

3 . The semiconductor memory device of claim 1 , wherein the buffer insulating layer has a rounded upper surface.

4 . The semiconductor memory device of claim 1 , wherein a sidewall of each of the lower electrodes is aligned with a sidewall of each of the lower contact plugs.

5 . The semiconductor memory device of claim 1 , wherein a sidewall of each of the lower electrodes is spaced apart from the sidewall of each of the magnetic tunnel junction patterns.

6 . The semiconductor memory device of claim 1 , wherein a lower surface of each of the lower electrodes is a first width and is in contact with an upper surface of each of the lower contact plugs, and
wherein an upper surface of each of the lower electrodes is a second width and in contact with a lower surface of each of the magnetic tunnel junction patterns, and wherein the first width is greater than the second width.

7 . The semiconductor memory device of claim 1 , wherein a center of each of the lower electrodes has a first thickness, and an edge of each of the lower electrodes has a second thickness, and
wherein the second thickness is smaller than the first thickness.

8 . The semiconductor memory device of claim 1 , wherein each of the lower electrodes comprises an upper portion in contact with each of the magnetic tunnel junction patterns and a lower portion in contact with each of the lower contact plugs,
wherein the lower portion of each of the lower electrodes has a first sidewall aligned with a sidewall of each of the lower contact plugs, and wherein the upper portion of each of the lower electrodes has a second sidewall aligned with the sidewall of each of the magnetic tunnel junction patterns.

9 . The semiconductor memory device of claim 1 , wherein the capping insulating layer is spaced apart from the interlayer insulating layer.

10 . A semiconductor memory device comprising:
a substrate; an interlayer insulating layer; a lower contact plug penetrating the interlayer insulating layer; a magnetic tunnel junction pattern connected to the lower contact plug; a lower electrode between the lower contact plug and the magnetic tunnel junction pattern; and an upper electrode on the magnetic tunnel junction pattern, wherein a first sidewall of the lower electrode is aligned with a sidewall of the lower contact plug and is spaced part from a sidewall of the magnetic tunnel junction pattern.

11 . The semiconductor memory device of claim 10 , wherein the lower electrode comprises a lower portion in contact with an upper surface of the lower contact plug and comprising the first sidewall, and the lower electrode comprises an upper portion in contact with a lower surface of the magnetic tunnel junction pattern, and
wherein the upper portion of the lower electrode has a second sidewall that is aligned with the sidewall of the magnetic tunnel junction pattern.

12 . The semiconductor memory device of claim 10 , wherein a width of a lower surface of the magnetic tunnel junction pattern is smaller than a width of a lower surface of the lower electrode.

13 . The semiconductor memory device of claim 10 , further comprising a buffer insulating layer on the first sidewall of the lower electrode on the interlayer insulating layer.

14 . The semiconductor memory device of claim 13 , wherein the buffer insulating layer has a rounded upper surface.

15 . The semiconductor memory device of claim 13 , wherein the buffer insulating layer comprises a metal element and oxygen.

16 . The semiconductor memory device of claim 10 , wherein a center of the lower electrode has a first thickness and an edge of the lower electrode has a second thickness smaller than the first thickness.

17 . A semiconductor memory device comprising:
a substrate; lower wiring lines on the substrate; an interlayer insulating layer on the lower wiring lines; lower contact plugs penetrating the interlayer insulating layer; magnetic tunnel junction patterns on the lower contact plugs, respectively; lower electrodes between the lower contact plugs and the magnetic tunnel junction patterns, respectively; a buffer insulating layer between the lower electrodes on the interlayer insulating layer; upper electrodes on the magnetic tunnel junction patterns, respectively; a capping insulating layer on a sidewall of each of the magnetic tunnel junction patterns and an upper surface of the buffer insulating layer; a buried insulating layer on the magnetic tunnel junction patterns on the capping insulating layer; and bit lines penetrating the buried insulating layer and connected to the upper electrodes, wherein the capping insulating layer is spaced apart from an upper surface of the interlayer insulating layer.

18 . The semiconductor memory device of claim 17 , wherein a lower surface of the capping insulating layer is at a level between an upper surface of each of the lower electrodes and a lower surface of each of the lower electrodes.

19 . The semiconductor memory device of claim 17 , wherein a sidewall of each of the lower electrodes is aligned with a sidewall of each of the lower contact plugs.

20 . The semiconductor memory device of claim 17 , wherein a sidewall of each of the lower electrodes has a first thickness and the upper surface of each of the lower contact plugs has a second thickness that is greater than the first thickness.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Hyunsung
• Byun Jihun

Classifications

• H10N50/10

  Magnetoresistive devices · CPC title

• H10N50/01

  Manufacture or treatment · CPC title

• H10B61/10 Primary

  comprising components having two electrodes, e.g. diodes or MIM elements · CPC title