Electronic Device

US2026090111A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2026090111-A1
Application numberUS-202519286233-A
CountryUS
Kind codeA1
Filing dateJul 30, 2025
Priority dateSep 23, 2024
Publication dateMar 26, 2026
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An electronic device includes a substrate, a first metal layer, a first insulating layer, a second metal layer, a third metal layer, an electronic component, a chip on film pad, and a flexible printed circuit pad. The substrate includes a first side and a second side. The first metal layer is disposed on the substrate. The first insulating layer is disposed on the first metal layer. The second metal layer is disposed on the first insulating layer. The third metal layer is disposed on the second metal layer. At least one portion of the third metal layer is configured to form at least one portion of an electrostatic discharge protection circuit. The electronic component includes a first terminal electrically connected to at least another portion of the third metal layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . An electronic device comprising: a substrate comprising: a first side; and a second side corresponding to the first side; a first metal layer disposed on the substrate; a first insulating layer disposed on the first metal layer; a second metal layer disposed on the first insulating layer; a third metal layer disposed on the second metal layer, wherein at least one portion of the third metal layer is configured to form at least one portion of an electrostatic discharge protection circuit; an electronic component comprising: a first terminal electrically connected to at least another portion of the third metal layer; a chip on film (COF) pad disposed on the first side of the substrate and electrically connected to the first metal layer and the second metal layer; and a flexible printed circuit (FPC) pad disposed on the second side of the substrate and electrically connected to at least another portion of the third metal layer. 2 . The electronic device of claim 1 , wherein the first metal layer has a first thickness, the second metal layer has a second thickness, the third metal layer has a third thickness, and the third thickness is greater than at least one of the first thickness and the second thickness. 3 . The electronic device of claim 1 , wherein a material of one of the second metal layer and the first metal layer is different from a material of the third metal layer. 4 . The electronic device of claim 1 , wherein a scan line of the electronic device is formed by one of the first metal layer and the second metal layer, a data line of the electronic device is formed by another one of the first metal layer and the second metal layer, the scan line and the data line are alternately disposed on the substrate for allocating a pixel unit, and one of the first metal layer and the second metal layer is configured to provide a data signal to the pixel unit. 5 . The electronic device of claim 4 , wherein the electronic component further comprises a second terminal, the pixel unit comprises a plurality of transistors, and one of the plurality of transistors is electrically connected to the second terminal of the electronic component. 6 . The electronic device of claim 4 , wherein the pixel unit comprises a plurality of transistors, each of the transistors comprises a gate terminal, a source terminal and, a drain terminal, one of the first metal layer and the second metal layer is electrically connected to the gate terminal, and another one of the first metal layer and the second metal layer is electrically connected to the source terminal and the drain terminal. 7 . The electronic device of claim 1 , wherein at least one portion of the electrostatic discharge protection circuit comprises at least one first electrostatic discharge trace. 8 . The electronic device of claim 7 , wherein the electrostatic discharge protection circuit further comprises a plurality of diode circuits, and the at least one first electrostatic discharge trace and the diode circuits form a portion of an electrostatic discharge protection ring. 9 . The electronic device of claim 7 , further comprising: a fourth metal layer disposed between the second metal layer and the third metal layer; wherein at least one second electrostatic discharge trace of the electrostatic discharge protection circuit is formed by at least one portion of the fourth metal layer, the electrostatic discharge protection circuit further comprises a plurality of diode circuits, and the at least one first electrostatic discharge trace, the at least one second electrostatic discharge trace, and the diode circuits are connected to form an electrostatic discharge protection ring. 10 . The electronic device of claim 1 , wherein at least a portion of the electrostatic discharge protection circuit comprises an inner electrostatic discharge trace and an outer electrostatic discharge trace, the inner electrostatic discharge trace and the outer electrostatic discharge trace are formed by the at least a portion of the third metal layer, the electrostatic discharge protection circuit comprises a plurality of diode circuits, the inner electrostatic discharge trace, and the outer electrostatic discharge trace are connected through the diode circuits, and the inner electrostatic discharge trace, the diode circuits, and the outer electrostatic discharge trace form an electrostatic discharge protection ring. 11 . The electronic device of claim 1 , wherein the third metal layer is electrically connected to the first metal layer through at least one portion of the second metal layer, the third metal layer is electrically connected to the first metal layer through at least another portion of the second metal layer, and the first metal layer is connected to a semiconductor material of at least one diode. 12 . The electronic device of claim 11 , wherein when the electronic device is affected by an electrostatic discharge current, the electrostatic discharge current is transmitted to the at least one diode through a first current leakage path and a second current leakage path, and a first equivalent resistance of the first current leakage path is greater than or equal to a second equivalent resistance of the second current leakage path. 13 . The electronic device of claim 12 , wherein the first current leakage path is configured to transmit the electrostatic discharge current from the first metal layer to the at least one diode, and the second current leakage path is configured to transmit the electrostatic discharge current from the first metal layer to the at least one diode through the at least one portion of the second metal layer, the third metal layer, and the at least another portion of the second metal layer. 14 . The electronic device of claim 1 , wherein a metal ring structure of the electrostatic discharge protection circuit comprises a first region and a second region, the first region is configured to block electrostatic discharge, and the second region is configured to avoid generating signal interferences. 15 . The electronic device of claim 14 , wherein the at least one portion of the third metal layer is electrically connected to the second metal layer and the first metal layer within the first region of the metal ring structure of the electrostatic discharge protection circuit. 16 . The electronic device of claim 15 , further comprising: a fourth metal layer disposed between the second metal layer and the third metal layer; wherein the fourth metal layer is electrically connected to at least one portion of the second metal layer, and electrically connected to the at least one portion of the third metal layer. 17 . The electronic device of claim 14 , further comprising: a fourth metal layer disposed between the second metal layer and the third metal layer; and a second insulating layer disposed between the second metal layer and the fourth metal layer; wherein the fourth metal layer and the second metal layer are electrically isolated within the second region of the metal ring structure of the electrostatic discharge protection circuit. 18 . The electronic device of claim 14 , further comprising: a fourth metal layer disposed between the second metal layer and the third metal layer; and a third insulating layer disposed between the third metal layer and the fourth metal layer; wherein the fourth metal layer and the third metal layer are electrically isolated within the second region of the metal ring structure of the electrostatic discharge protect

Assignees

Inventors

Classifications

  • Interconnections (of active-matrix LED displays H10H29/49) · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • adapted for preventing breakage, peeling or short circuiting · CPC title

  • H10D89/611Primary

    using diodes as protective elements · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2026090111A1 cover?
An electronic device includes a substrate, a first metal layer, a first insulating layer, a second metal layer, a third metal layer, an electronic component, a chip on film pad, and a flexible printed circuit pad. The substrate includes a first side and a second side. The first metal layer is disposed on the substrate. The first insulating layer is disposed on the first metal layer. The second …
Who is the assignee on this patent?
Innolux Corp
What technology area does this patent fall under?
Primary CPC classification H10D89/611. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Mar 26 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).