Semiconductor device with field plate structure

Patent metadata

Field	Value
Publication number	US-2026090054-A1
Application number	US-202519324418-A
Country	US
Kind code	A1
Filing date	Sep 10, 2025
Priority date	Sep 26, 2024
Publication date	Mar 26, 2026
Grant date	—

Abstract

A semiconductor device includes a substrate, an insulator layer, and a field plate structure. The substrate has a background doping of a first conductivity type and includes a first doped region of a second conductivity type complementary to the first conductivity type. The insulator layer is formed on a main surface of the substrate. The field plate structure is formed on the insulator layer between the first doped region and an edge structure. The field plate structure has a high-resistive and/or semi-insulating connection with at least one non-floating conductive structure.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate having a background doping of a first conductivity type and comprising a first doped region of a second conductivity type complementary to the first conductivity type; an insulator layer on a main surface of the substrate; and a field plate structure on the insulator layer between the first doped region and an edge structure, wherein the field plate structure has a high-resistive and/or semi-insulating connection with at least one non-floating conductive structure.

2 . The semiconductor device of claim 1 ,
wherein the non-floating conductive structure includes a contact structure, wherein the contact structure forms an ohmic contact with one of the first doped region and a second doped region, and wherein the second doped region forms part of the edge structure.

3 . The semiconductor device of claim 1 ,
wherein the non-floating conductive structure includes a contact structure, wherein the contact structure forms an ohmic contact with a first doped device region and/or a second doped device region of a semiconductor layer on the insulator layer.

4 . The semiconductor device of claim 1 ,
wherein the high-resistive and/or semi-insulating connection comprises a charge shielding layer in direct contact with the field plate structure and the non-floating contact structure.

5 . The semiconductor device of claim 4 ,
wherein the charge shielding layer is formed directly on the field plate structure.

6 . The semiconductor device of claim 4 , further comprising:
an insulating passivation layer on the charge shielding layer.

7 . The semiconductor device of claim 6 , further comprising:
a separation layer separating the charge shielding layer and the passivation layer.

8 . The semiconductor device of claim 4 ,
wherein the field plate structure comprises a metal portion, and wherein the charge shielding layer is formed directly on the metal portion.

9 . The semiconductor device of claim 4 ,
wherein the field plate structure comprises a polysilicon portion formed from doped polycrystalline silicon, and wherein the charge shielding layer is formed directly on the polysilicon portion.

10 . The semiconductor device of claim 4 ,
wherein the field plate structure comprises a polycrystalline portion at a distance from the main surface and a metal portion in direct contact with the polycrystalline portion at a side of the polycrystalline portion opposite to the substrate, and wherein the charge shielding layer is formed directly on the metal portion.

11 . The semiconductor device of claim 1 , further comprising:
a voltage transition structure in the substrate between the first doped region and the edge structure, wherein the voltage transition structure is configured to reduce a maximum electric field in the substrate when a voltage is present between the first doped region and the edge structure.

12 . The semiconductor device of claim 11 ,
wherein the voltage transition structure laterally surrounds the first doped region.

13 . The semiconductor device of claim 1 ,
wherein the field plate structure laterally surrounds the first doped region.

14 . The semiconductor device of claim 1 ,
wherein the edge structure comprises a lateral outer surface of the substrate.

15 . The semiconductor device of claim 1 , further comprising:
a semiconductor layer on the insulator layer; and a first interlayer dielectric on the semiconductor layer, wherein the field plate structure is formed on the first interlayer dielectric.

16 . The semiconductor device of claim 15 , further comprising:
a first metallization structure directly on the first interlayer dielectric; and a second interlayer dielectric directly on the first metallization structure, wherein the field plate structure comprises a first portion formed from a field portion of the first metallization structure and a second portion formed on the second interlayer dielectric.

17 . The semiconductor device of claim 16 ,
wherein the field plate structure further comprises a plurality of laterally separated field plate portions, wherein the first metallization layer comprises a plurality of laterally separated tile portions, and wherein each tile portion of the first metallization layer is electrically connected with at least one of the field plate portions.

18 . The semiconductor device of claim 17 ,
wherein the tile portions are formed in gaps between the field plate portions.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Winterer Felix Simon
• Künzig Thomas
• Schippel Christian
• Priefert Dirk
• Sidelnicov Andrei

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H03K17/04126

  in bipolar transistor switches · CPC title

• H03K17/04123

  in field-effect transistor switches · CPC title

• H03K17/0406

  in composite switches · CPC title

• H10D1/472

  having an active material comprising carbon, e.g. diamond or diamond-like carbon [DLC] · CPC title