Managing program time in memory devices

Patent metadata

Field	Value
Publication number	US-2026088090-A1
Application number	US-202418911190-A
Country	US
Kind code	A1
Filing date	Oct 9, 2024
Priority date	Sep 20, 2024
Publication date	Mar 26, 2026
Grant date	—

Abstract

Methods, devices, and systems for managing memory devices are provided. In one aspect, a method includes, during a first loop of a program operation, applying a first program voltage to a first word line, applying, to a second word line, a first pass voltage during a first stage and a second pass voltage during a second stage; during a second loop, applying a second program voltage to the first word line, applying, to the second word line, a third pass voltage during a first stage and a fourth pass voltage during a second stage; and during a third loop, applying a third program voltage to the first word line, applying, to the second word line, a fifth pass voltage during a first stage and a sixth pass voltage during a second stage. The third pass voltage is lower than the first pass voltage and the fifth pass voltage.

First claim

What is claimed is:

1 . A method of programming a memory device, comprising:
during a first loop of a first program operation to program memory cells coupled to a first word line:
applying a first program voltage to the first word line;
applying, during a first stage of the first loop, a first pass voltage to at least one second word line; and
applying, during a second stage of the first loop, a second pass voltage to the at least one second word line, wherein the second stage is after the first stage; and
during a second loop of the first program operation:
applying a second program voltage to the first word line;
applying, during a first stage of the second loop, a third pass voltage to the at least one second word line; and
applying, during a second stage of the second loop, a fourth pass voltage to the at least one second word line,
during a third loop of the first program operation:
applying a third program voltage to the first word line;
applying, during a first stage of the third loop, a fifth pass voltage to the at least one second word line; and
applying, during a second stage of the third loop, a sixth pass voltage to the at least one second word line,
wherein the second loop is after the first loop, the third loop is after the second loop, the second program voltage is higher than the first program voltage, and the third program voltage is higher than the second program voltage, and wherein the third pass voltage is lower than the first pass voltage, and the fifth pass voltage is higher than the third pass voltage.

2 . The method of claim 1 , wherein the memory device comprises word lines numbered in sequence, and
wherein the first word line is the n th word line of the word lines, the at least one second word line comprises at least one of the (n+1) th or the (n−1) th word line of the word lines, where n is a positive integer.

3 . The method of claim 1 , wherein the second pass voltage, the fourth pass voltage and the sixth pass voltage are identical.

4 . The method of claim 1 , wherein a difference between the second pass voltage and the first pass voltage is smaller than a difference between the fourth pass voltage and the third pass voltage, and the difference between the fourth pass voltage and the third pass voltage is greater than a difference between the sixth pass voltage and the fifth pass voltage.

5 . The method of claim 1 , wherein a first voltage of the first word line during the first stage of the second loop is lower than a second voltage of the first word line during the second stage of the second loop.

6 . The method of claim 1 , comprising:
applying, during a first stage of a fourth loop of the first program operation, the fifth pass voltage to the at least one second word line, wherein the fourth loop is after the third loop.

7 . The method of claim 1 , comprising:
during a first loop of a second program operation to program memory cells coupled to a third word line:
applying a fourth program voltage to the third word line;
applying, during a first stage of the first loop of the second program operation, a seventh pass voltage to at least one fourth word line; and
applying, during a second stage of the first loop of the second program operation, an eighth pass voltage to the at least one fourth word line, wherein the second stage is after the first stage;
during a second loop of the second program operation:
applying a fifth program voltage to the third word line;
applying, during a first stage of the second loop of the second program operation, a ninth pass voltage to the at least one fourth word line; and
applying, during a second stage of the second loop of the second program operation, a tenth pass voltage to the at least one fourth word line; and
during a third loop of the second program operation:
applying a sixth program voltage to the third word line;
applying, during a first stage of the third loop of the second program operation, an eleventh pass voltage to the at least one fourth word line; and
applying, during a second stage of the third loop of the second program operation, a twelfth pass voltage to the at least one fourth word line,
wherein the first loop, the second loop, and the third loop of the second program operation are sequential to each other, and wherein the fifth program voltage is higher than the fourth program voltage, and the sixth program voltage is higher than the fifth program voltage, and wherein a difference between the eighth pass voltage and the seventh pass voltage, a difference between the tenth pass voltage and the ninth pass voltage, and a difference between the twelfth pass voltage and the eleventh pass voltage are identical to each other.

8 . The method of claim 7 , wherein the seventh pass voltage, the ninth pass voltage and the eleventh pass voltage are identical to each other, and
wherein the eighth pass voltage, the tenth pass voltage and the twelfth pass voltage are identical to each other.

9 . The method of claim 7 , wherein the ninth pass voltage is higher than the seventh pass voltage, and the eleventh pass voltage is higher than the ninth pass voltage, and
wherein the tenth pass voltage is higher than the eighth pass voltage, and the twelfth pass voltage is higher than the tenth pass voltage.

10 . The method of claim 7 , wherein the memory device comprises word lines numbered in sequence, and
wherein the third word line is the m th word line of the word lines, the at least one fourth word line comprises at least one of the (m+1) th or the (m−1) th word line of the word lines, where m is a positive integer.

11 . The method of claim 7 , wherein the memory device comprises word lines in sequence from a first side to a second side along a direction, and the word lines of the memory device comprise a first set of word lines and a second set of word lines, wherein the second set of word lines are closer to the second side of the memory device than the first set of word lines along the direction, and
wherein the first set of word lines comprises the first word line, and the second set of word lines comprises the third word line.

12 . The method of claim 11 , wherein the second set of word lines comprise about 10 word lines.

13 . The method of claim 7 , wherein a deck of the memory device comprises a first side and a second side along a direction, and word lines of the deck comprise a third set of word lines and a fourth set of word lines, wherein the third set of word lines are closer to the first side of the deck than the fourth set of word lines, and
wherein the third set of word lines comprises the third word line, and the fourth set of word lines comprises the first word line.

14 . The method of claim 13 , wherein the third set of word lines comprise about 10 word lines.

15 . A memory device, comprising:
a memory array comprising a first word line and at least one second word line; and a peripheral circuit coupled to the memory array, wherein the peripheral circuit is configured to perform operations comprising:
during a first loop of a first program operation to program memory cells coupled to the first word line:
applying a first program voltage to the first word line;
applying, during a first stage of the first loop, a first pass voltage to the at least one second word line; and
applying, during a second stage of the first loop, a second pass voltage to the at least one second word line, wherein the second stage is after the first stage; and

during a second loop of the first program operation:
applying a second program voltage to the fi

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Qi Wei
• Ji Guoqi
• Nie Yong
• Li Da

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title