Apparatus and method for scheduling i/o requests input along with overlapped address for parallel processing in memory system

Patent metadata

Field	Value
Publication number	US-2026086738-A1
Application number	US-202519062016-A
Country	US
Kind code	A1
Filing date	Feb 25, 2025
Priority date	Sep 23, 2024
Publication date	Mar 26, 2026
Grant date	—

Abstract

A memory system includes a memory device and a controller. The memory device includes at least one storage region. The controller is coupled to the memory device. The controller is configured to transmit to the memory device a command used for storing data in the at least one storage region or reading stored data from the at least one storage region. The controller is configured to differently perform scheduling, based on whether addresses, input along with at least two commands belonging to a preset range of commands to be transmitted to the memory device, are overlapped, so that a first order in which the commands are input from an external device is equal to a second order in which the commands are transmitted to the memory device.

First claim

What is claimed is:

1 . A memory system comprising:
a memory device comprising at least one storage region; and a controller coupled to the memory device and configured to transmit to the memory device a command used for storing data in the at least one storage region or reading stored data from the at least one storage region, wherein the controller is configured to differently perform scheduling, based on whether addresses, input along with at least two commands belonging to a preset range of commands to be transmitted to the memory device, are overlapped, so that a first order in which the commands are input from an external device is equal to a second order in which the commands are transmitted to the memory device.

2 . The memory system according to claim 1 , wherein the controller is configured to compare addresses corresponding to a specific command with addresses corresponding to at least one of a first command and a second command to determine whether the addresses are overlapped, the first command input immediately before the specific command, the second command input immediately after the specific command.

3 . The memory system according to claim 2 , wherein the controller is configured to transmit to the memory device the specific command after transmitting the first command when at least one of the addresses corresponding to the specific command is equal to at least one of the addresses corresponding to the first command.

4 . The memory system according to claim 2 , wherein the controller is configured to transmit to the memory device the specific command before transmitting the second command when at least one of the addresses corresponding to the specific command is equal to at least one of the addresses corresponding to the second command.

5 . The memory system according to claim 2 , wherein the controller is configured to change a transmitting order of the specific command, the first command, and the second command, based on a type of the specific command, the first command, and the second command, when none of the addresses corresponding to the specific command is equal to the addresses corresponding to the first command or the addresses corresponding to the second command.

6 . The memory system according to claim 1 , wherein the controller is configured to determine whether to perform the scheduling regardless of types of the commands.

7 . The memory system according to claim 1 , wherein the controller comprises:
a command range blocker configured to determine whether to process or handle the commands; a command fetcher configured to determine whether the addresses are overlapped, after receiving the commands transmitted from the command range blocker, and transmit the commands to different paths based on types of the commands; a write processing unit configured to receive a write command from the command fetcher and process or handle the write command; a read processing unit configured to receive a read command from the command fetcher and process or handle the read command; and a buffer configured to store the write or read command transmitted from the write processing unit or the read processing unit, sequentially transmit the stored write or read command to the memory device, and link a response transmitted from the memory device with the transmitted write or read command.

8 . The memory system according to claim 7 , wherein the command fetcher is further configured to assign a number to a command transmitted from the command range blocker according to a transmitting order based on whether the addresses are overlapped,
wherein the controller further comprises a command counter configured to: check the number assigned to the command which is to be processed by the write processing unit or the read processing unit; and adjust or change an order of processing the command in the write processing unit or the read processing unit based on the first order.

9 . The memory system according to claim 7 ,
wherein the command fetcher is configured to request the command range blocker to block transmission of one of the read command or the write command based on whether the addresses are overlapped, and wherein the command range blocker is configured to block the transmission of one of the read command or the write command based on a request of the command fetcher.

10 . The memory system according to claim 7 ,
wherein the addresses comprise logical addresses used by the external device, and wherein each of the write processing unit and the read processing unit comprises a Flash Translation Layer (FTL).

11 . A method for operating a memory system, the method comprising:
determining whether addresses, input along with at least two commands belonging to a preset range of commands to be transmitted to the memory device, are overlapped; performing scheduling, so that a first order in which the commands are input from an external device is equal to a second order in which the commands are transmitted to the memory device, when the addresses are overlapped; processing the commands without the scheduling when the addresses are not overlapped; and sequentially transmitting processed or scheduled commands to a memory device.

12 . The method according to claim 11 , wherein the determining whether the addresses are overlapped comprises:
comparing addresses corresponding to a specific command with addresses corresponding to at least one of a first command and a second command, the first command input immediately before the specific command, the second command input immediately after the specific command; and determining whether the addresses are overlapped based on a comparison result.

13 . The method according to claim 12 , wherein the performing scheduling comprises:
transmitting the specific command to the memory device after transmitting the first command based on the comparison result; and transmitting the specific command to the memory device before transmitting the second command based on the comparison result.

14 . The method according to claim 12 , wherein the processing the commands comprises:
processing the specific command, the first command, and the second command based on types of the specific command, the first command, and the second command regardless of an input order of the specific command, the first command, and the second command.

15 . The method according to claim 11 , wherein the performing the scheduling comprises:
assigning a number according to an input order to each of the commands based on whether the addresses are overlapped; and sequentially processing each of the commands based on an assigned number.

16 . The method according to claim 11 , wherein the performing the scheduling comprises:
suspending transmission of one of a read command and a write command based on whether the addresses are overlapped.

17 . A memory system comprising:
a memory device storing data; and a controller configured to make a first order in which read commands and write commands are input from an external device and a second order in which the read commands and the write commands are transmitted to the memory device to be identical when at least one of addresses input along with the read commands and the write commands is overlapped, while processing the read commands and the write commands to be transmitted to the memory device through separate paths in the controller.

18 . The memory system according to claim 17 , wherein the controller is configured to transmit the read command

Assignees

• Sk Hynix Inc

Inventors

• Kim Ki Tae

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title