Apparatus and method for testing a semiconductor package

US2026086113A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2026086113-A1
Application numberUS-202519334995-A
CountryUS
Kind codeA1
Filing dateSep 22, 2025
Priority dateSep 23, 2024
Publication dateMar 26, 2026
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus for testing a semiconductor package comprises: a test board; an adaptor socket disposed on and electrically coupled to the test board; a first reference module and a second reference module each being removably seated in the reference seat of the adaptor socket; and a test socket disposed on the adaptor socket. The test socket comprises: a socket body having a test seat for seating the semiconductor package, and defining together with the adaptor socket a lower cavity below the test seat and for accommodating the first reference module or the second reference module; and contact pins vertically extending through the socket body between the test seat and the lower cavity and movable vertically relative to the socket body.

First claim

Opening claim text (preview).

1 . An apparatus for testing a semiconductor package, wherein the semiconductor package comprises at least a first semiconductor component and a second semiconductor component and a mold cap encapsulating the first and second semiconductor components, wherein the first semiconductor component has a first set of conductive pads exposed from the mold cap, and the second semiconductor component has a second set of conductive pads exposed from the mold cap, and wherein the apparatus comprises: a test board; an adaptor socket disposed on and electrically coupled to the test board, wherein the adaptor socket has a reference seat; a first reference module and a second reference module each being removably seated in the reference seat of the adaptor socket so as to be electrically coupled to the test board through the adaptor socket, wherein the first reference module comprises a first base substrate with a first set of test pads and a second reference semiconductor component mounted on the first base substrate in a layout as the second semiconductor component of the semiconductor package, and the second reference module comprises a second base substrate with a second set of test pads and a first reference semiconductor component mounted on the second base substrate in a layout as the first semiconductor component of the semiconductor package; and a test socket disposed on the adaptor socket, wherein the test socket comprises: a socket body having a test seat for seating the semiconductor package, and defining together with the adaptor socket a lower cavity below the test seat and for accommodating the first reference module or the second reference module, such that the first set of test pads of the first reference module are vertically aligned with the first set of conductive pads of the first semiconductor component or the second set of test pads of the second reference module are vertically aligned with the second set of conductive pads of the second semiconductor component when the semiconductor package is seated in the test seat; and contact pins vertically extending through the socket body between the test seat and the lower cavity and movable vertically relative to the socket body, wherein when the semiconductor package is under test, the contact pins are pressed by the semiconductor package against the first reference module or the second reference module to set up an electrical connection between the first set of conductive pads of the first semiconductor component and the first set of test pads of the first reference module or between the second set of conductive pads of the second semiconductor component and the second set of test pads of the second reference module. 2 . The apparatus of claim 1 , further comprising: a socket lid disposed above the test socket and the semiconductor package, wherein the socket lid is configured for pushing the semiconductor package towards the test socket. 3 . The apparatus of claim 2 , wherein the contact pins comprise pogo pins. 4 . The apparatus of claim 1 , further comprising: a fastener assembly disposed between the adaptor socket and the test socket, and configured for assembling the adaptor socket with the test socket. 5 . The apparatus of claim 1 , wherein the adaptor socket is electrically coupled to the test board through contact pins. 6 . The apparatus of claim 1 , wherein the test socket comprises a step structure configured for pressing adaptor socket and the first or second reference module when it is placed on the adaptor socket. 7 . A method for testing a semiconductor package, wherein the semiconductor package comprises at least a first semiconductor component and a second semiconductor component and a mold cap encapsulating the first and second semiconductor components, wherein the first semiconductor component has a first set of conductive pads exposed from the mold cap, and the second semiconductor component has a second set of conductive pads exposed from the mold cap; and wherein the method comprises: providing a first reference module and a second reference module, wherein the first reference module comprises a first base substrate with a first set of test pads and a second reference semiconductor component mounted on the first base substrate in a layout as the second semiconductor component of the semiconductor package, and the second reference module comprises a second base substrate with a second set of test pads and a first reference semiconductor component mounted on the second base substrate in a layout as the first semiconductor component of the semiconductor package; providing a test board with an adaptor socket disposed thereon, wherein the adaptor socket is electrically coupled to the test board and has a reference seat; placing the first reference module in the reference seat of the adaptor socket such that the first reference module is electrically coupled to the test board via the adaptor socket; placing a test socket on the adaptor socket, wherein the test socket comprises a socket body having a test seat and defining together with the adaptor socket a lower cavity below the test seat, and contact pins vertically extending through the socket body between test seat and the lower cavity and movable relative to the socket body, and wherein the first reference module is accommodated within the lower cavity; placing the semiconductor package in the test seat of the test socket to set up an electrical connection between the first set of conductive pads of the first semiconductor component and the first set of test pads of the first reference module; removing the semiconductor package, the test socket and the first reference module from the adaptor socket; placing the second reference module in the reference seat of the adaptor socket such that the second reference module is electrically coupled to the test board via the adaptor socket; placing the test socket on the adaptor socket to accommodate the second reference module in the lower cavity; and placing the semiconductor package in the test seat of the test socket to set up an electrical connection between the second set of conductive pads of the second semiconductor component and the second set of test pads of the second reference module. 8 . The method of claim 7 , wherein placing the semiconductor package in the test seat of the test socket further comprises: pushing the semiconductor package towards the test socket via a socket lid disposed above the socket body and the semiconductor package. 9 . The method of claim 7 , wherein the contact pins comprise pogo pins. 10 . An apparatus for testing a semiconductor package, wherein the semiconductor package comprises a plurality of semiconductor components and a mold cap encapsulating the plurality of semiconductor components, wherein each of the plurality of semiconductor components has a set of conductive pads exposed from the mold cap, and wherein the apparatus comprises: a test board; an adaptor socket disposed on and electrically coupled to the test board, wherein the adaptor socket has a reference seat; a plurality of reference modules each being removably seated in the reference seat of the adaptor socket so as to be electrically coupled to the test board through the adaptor socket; wherein each of the plurality of reference modules comprises a base substrate with a set of test pads corresponding to a target semiconductor component of the plurality of semiconductor components of the semiconductor package, and a set of reference semiconductor components mounted on the base substrate in a layout as all non-target semiconductor components of the plurality of semiconductor components of the semiconductor package; and a test socket

Assignees

Inventors

Classifications

  • Contacting devices, e.g. sockets, burn-in boards or mounting fixtures (in general G01R1/04) · CPC title

  • Testing of IC packages; Test features related to IC packages (containers per se H10W76/10, encapsulations per se H10W74/00) · CPC title

  • G01R1/0466Primary

    concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding · CPC title

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What does patent US2026086113A1 cover?
An apparatus for testing a semiconductor package comprises: a test board; an adaptor socket disposed on and electrically coupled to the test board; a first reference module and a second reference module each being removably seated in the reference seat of the adaptor socket; and a test socket disposed on the adaptor socket. The test socket comprises: a socket body having a test seat for seating…
Who is the assignee on this patent?
Jcet Stats Chippac Korea Ltd
What technology area does this patent fall under?
Primary CPC classification G01R1/0466. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Mar 26 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).