Semiconductor device

Patent metadata

Field	Value
Publication number	US-2026082872-A1
Application number	US-202519396573-A
Country	US
Kind code	A1
Filing date	Nov 21, 2025
Priority date	Oct 30, 2009
Publication date	Mar 19, 2026
Grant date	—

Abstract

An object is to provide a semiconductor device with reduced standby power. A transistor including an oxide semiconductor as an active layer is used as a switching element, and supply of a power supply voltage to a circuit in an integrated circuit is controlled by the switching element. Specifically, when the circuit is in an operation state, supply of the power supply voltage to the circuit is performed by the switching element, and when the circuit is in a stop state, supply of the power supply voltage to the circuit is stopped by the switching element. In addition, the circuit supplied with the power supply voltage includes a semiconductor element which is a minimum unit included in an integrated circuit formed using a semiconductor. Further, the semiconductor included in the semiconductor element contains silicon having crystallinity (crystalline silicon).

First claim

1 . (canceled)

2 . A display device comprising:
a first transistor including a first channel formation region comprising silicon; a second transistor including a second channel formation region comprising silicon; a third transistor including a third channel formation region located over the first channel formation region and the second channel formation region; a first conductive film including a region located over the first channel formation region and configured to be a gate electrode of the first transistor; a second conductive film including a region located over the second channel formation region and configured to be a gate electrode of the second transistor; a first insulating film provided over the first conductive film and the second conductive film; a third conductive film including a region in contact with a top surface of the first insulating film and configured to be a gate electrode of the third transistor; a fourth conductive film including a region in contact with the top surface of the first insulating film, the fourth conductive film comprising a same material as the third conductive film; a second insulating film provided over the third conductive film and the fourth conductive film; an oxide semiconductor film provided over the second insulating film and including a region configured to be the third channel formation region; a fifth conductive film including a region in contact with a top surface of the oxide semiconductor film, the fifth conductive film being electrically connected to one of a a sixth conductive film including a region in contact with a top surface of the fourth conductive film, the sixth conductive film being electrically connected to one of a source region and a drain region of the second transistor and comprising a same material as the fifth conductive film; and a third insulating film provided over the fifth conductive film and the sixth conductive film, wherein the fourth conductive film is configured to be a wiring, and wherein the oxide semiconductor film comprises at least indium.

3 . The display device according to claim 2 , wherein each of the first channel formation region and the second channel formation region comprises any one of microcrystalline silicon, polycrystalline silicon, and single crystal silicon.

4 . The display device according to claim 2 , wherein the oxide semiconductor film further comprises gallium and zinc.

5 . The display device according to claim 2 , further comprising a seventh conductive film overlapping the oxide semiconductor film with the third insulating film provided therebetween.

6 . The display device according to claim 2 , further comprising a light-emitting element.

7 . An electronic equipment comprising:
the display device according to claim 2 ; and a housing.

8 . A mobile phone comprising:
the display device according to claim 2 ; a housing; an audio-input portion; an audio-output portion; and a light-receiving portion.

9 . A display device comprising:
a first transistor including a first channel formation region comprising silicon; a second transistor including a second channel formation region comprising silicon; a third transistor including a third channel formation region located over the first channel formation region and the second channel formation region; a first conductive film including a region located over the first channel formation region and configured to be a gate electrode of the first transistor; a second conductive film including a region located over the second channel formation region and configured to be a gate electrode of the second transistor; a first insulating film including at least a first region located over the first conductive film and a second region located over the second conductive film; a third conductive film including a region in contact with a top surface of the first insulating film and configured to be a gate electrode of the third transistor; a fourth conductive film including a region in contact with the top surface of the first insulating film, the fourth conductive film comprising a same material as the third conductive film; a second insulating film including a first region located over the third conductive film and a second region located over the fourth conductive film; an oxide semiconductor film provided over the second insulating film and including a region configured to be the third channel formation region; a fifth conductive film including a first region in contact with a top surface of the oxide semiconductor film and a second region in contact with one of a source region and a drain region of the first transistor; a sixth conductive film including a first region in contact with a top surface of the fourth conductive film and a second region in contact with one of a source region and a drain region of the second transistor, the sixth conductive film comprising a same material as the fifth conductive film; and a third insulating film including a first region in contact with a top surface of the fifth conductive film and a second region in contact with a top surface of the sixth conductive film, wherein the fourth conductive film is configured to be a wiring, and wherein the oxide semiconductor film comprises at least indium.

10 . The display device according to claim 9 , wherein each of the first channel formation region and the second channel formation region comprises any one of microcrystalline silicon, polycrystalline silicon, and single crystal silicon.

11 . The display device according to claim 9 , wherein the oxide semiconductor film further comprises gallium and zinc.

12 . The display device according to claim 9 , further comprising a seventh conductive film overlapping the oxide semiconductor film with the third insulating film provided therebetween.

13 . The display device according to claim 9 , further comprising a light-emitting element.

14 . An electronic equipment comprising:
the display device according to claim 9 ; and a housing.

15 . A mobile phone comprising:
the display device according to claim 9 ; a housing; an audio-input portion; an audio-output portion; and a light-receiving portion.

16 . A display device comprising:
a first transistor including a first channel formation region comprising polycrystalline silicon; a second transistor including a second channel formation region comprising polycrystalline silicon; a third transistor including a third channel formation region located over the first channel formation region and the second channel formation region; a first conductive film including a region located over the first channel formation region and configured to be a gate electrode of the first transistor; a second conductive film including a region located over the second channel formation region and configured to be a gate electrode of the second transistor; a first insulating film provided over the first conductive film and the second conductive film; a third conductive film including a region in contact with a top surface of the first insulating film and configured to be a gate electrode of the third transistor; a fourth conductive film including a region in contact with the top surface of the first insulating film, the fourth conductive film comprising a same material as the third conductive film; a second insulating film provided over the third conductive film and the fourth conductive film; an oxide semiconductor film provided over the second insulating film and including a region configured to be the third channel formation regi

Assignees

• Semiconductor Energy Lab

Inventors

• Shionoiri Yutaka
• Noda Kosei

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10P90/1916 Primary

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title