Electronic device package and fabricating method thereof
US-2024347575-A1 · Oct 17, 2024 · US
Image sensor device
US2026082717A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2026082717-A1 |
| Application number | US-202519195311-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 30, 2025 |
| Priority date | Dec 11, 2014 |
| Publication date | Mar 19, 2026 |
| Grant date | — |
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- Title
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Abstract
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Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.
First claim
Opening claim text (preview).
1 . A method, comprising: obtaining an image sensor wafer having a first dielectric layer with a first surface; obtaining a reconstituted wafer having a processor die and a second dielectric layer with a second surface; and bonding the reconstituted wafer and the image sensor wafer to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer.
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between stacked chips · CPC title
on encapsulations · CPC title
On different surfaces · CPC title
Dispositions, e.g. layouts · CPC title
comprising holes having chips therein · CPC title
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Frequently asked questions
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- What does patent US2026082717A1 cover?
- Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonde…
- Who is the assignee on this patent?
- Adeia Semiconductor Tech Llc
- What technology area does this patent fall under?
- Primary CPC classification H10F39/804. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Mar 19 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).