Memory system

Patent metadata

Field	Value
Publication number	US-2026079629-A1
Application number	US-202519067802-A
Country	US
Kind code	A1
Filing date	Feb 28, 2025
Priority date	Sep 17, 2024
Publication date	Mar 19, 2026
Grant date	—

Abstract

A memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a plurality of physical full blocks. Each of the plurality of physical full blocks includes a plurality of physical sub-blocks. The memory controller executes a data erase operation independently for each of the plurality of physical sub-blocks in each of the plurality of physical full blocks, and in each of the plurality of physical full blocks, sets all of the plurality of physical sub-blocks therein to a same storage mode. The storage mode set for a physical sub-block indicates the number of bits of data stored in a memory cell thereof.

First claim

What is claimed is:

1 . A memory system comprising:
a nonvolatile memory that includes a plurality of physical full blocks, each of the plurality of physical full blocks including a plurality of physical sub-blocks; and a memory controller that is electrically connected to the nonvolatile memory, and configured to:
execute a data erase operation independently for each of the plurality of physical sub-blocks in each of the plurality of physical full blocks; and
in each of the plurality of physical full blocks, set all of the plurality of physical sub-blocks therein to a same storage mode, wherein
the storage mode set for a physical sub-block indicates the number of bits of data stored in a memory cell thereof.

2 . The memory system according to claim 1 , wherein
the plurality of physical full blocks includes at least a first physical full block and a second physical full block, and each of the plurality of physical full blocks includes at least a first physical sub-block and a second physical sub-block, and the memory controller is further configured to:
manage the first physical sub-block of the first physical full block and the first physical sub-block of the second physical full block as a first logical sub-block;
manage the second physical sub-block of the first physical full block and the second physical sub-block of the second physical full block as a second logical sub-block;
set the same storage mode to all the logical sub-blocks in the first logical sub-block including the first physical sub-block of the first physical full block and the first physical sub-block of the second physical full block; and
set the same storage mode to all the logical sub-blocks in the second logical sub-block including the second physical sub-block of the first physical full block and the second physical sub-block of the second physical full block.

3 . The memory system according to claim 2 , wherein
the memory controller is further configured to:
execute the data erase operation, collectively, on all the logical sub-blocks in the first logical sub-block including the first physical sub-block of the first physical full block and the first physical sub-block of the second physical full block; and
execute the data erase operation, collectively, on all the logical sub-blocks in the second logical sub-block including the second physical sub-block of the first physical full block and the second physical sub-block of the second physical full block.

4 . The memory system according to claim 2 , wherein
the memory controller is further configured to:
manage, as a first logical full block, a set that includes the first logical sub-block and the second logical sub-block; and
execute the data erase operation, collectively, on the first logical sub-block and the second logical sub-block, which are provided in the first logical full block.

5 . The memory system according to claim 1 , wherein
the memory controller is further configured to:
manage a plurality of logical full blocks, each of which includes at least two physical full blocks among the plurality of physical full blocks;
manage a plurality of logical sub-blocks, each of which includes at least two physical sub-blocks among the plurality of physical sub-blocks; and
in each of the plurality of logical sub-blocks, set the at least two physical sub-blocks provided therein to the same storage mode, and
the number of the plurality of physical sub-blocks provided in each of the plurality of physical full blocks is equal to the number of the plurality of logical sub-blocks provided in each of the plurality of logical full blocks.

6 . The memory system according to claim 1 , wherein
the memory controller is further configured to:
manage a plurality of logical full blocks, each of which includes at least two physical full blocks among the plurality of physical full blocks;
manage a plurality of logical sub-blocks, each of which includes at least two physical sub-blocks among the plurality of physical sub-blocks; and
in each of the plurality of logical sub-blocks, set all of the at least two physical sub-blocks provided therein to the same storage mode, and
all of the at least two physical sub-blocks provided in each of the plurality of logical sub-blocks are included in only one of the plurality of logical full blocks.

7 . The memory system according to claim 1 , wherein
the memory controller is further configured to:
manage a plurality of logical full blocks, each of which includes at least two physical full blocks among the plurality of physical full blocks;
manage a plurality of logical sub-blocks, each of which includes at least two physical sub-blocks among the plurality of physical sub-blocks; and
select a logical full block or a logical sub-block to be a target of garbage collection based on at least valid data ratios of the plurality of logical full blocks and valid data ratios of the plurality of logical sub-blocks.

8 . The memory system according to claim 7 , wherein
the plurality of logical sub-blocks includes at least a first logical sub-block set to a first storage mode, the plurality of logical full blocks includes at least a first logical full block set to a second storage mode different from the first storage mode, and the memory controller is further configured to:
compare a first valid data ratio which is the valid data ratio of the first logical sub-block, with a second valid data ratio which is the valid data ratio of the first logical full block;
select the first logical sub-block as the target of the garbage collection when the first valid data ratio is equal to or smaller than the second valid data ratio; and
select the first logical full block as the target of the garbage collection when the first valid data ratio is greater than the second valid data ratio.

9 . The memory system according to claim 8 , wherein
the memory controller is further configured to, when the first valid data ratio is equal to or smaller than the second valid data ratio,
copy, in the first storage mode, valid data from the first logical sub-block to a physical sub-block, which is not provided in the first logical sub-block among the plurality of physical sub-blocks; and
execute the data erase operation in the first storage mode on the first logical sub-block after copying the valid data.

10 . The memory system according to claim 8 , wherein
the memory controller is further configured to, when the first valid data ratio is greater than the second valid data ratio,
copy, in the second storage mode, valid data from the first logical full block to a physical sub-block in a physical full block, which is not provided in the first logical full block among the plurality of physical full blocks; and
execute the data erase operation in the first storage mode on the first logical full block after copying the valid data.

11 . The memory system according to claim 8 , wherein
the memory controller is further configured to:
determine the number of logical sub-blocks in which valid data is not stored among logical sub-blocks set to the first storage mode; and
in response to the number being equal to or smaller than a first threshold value, compare the first valid data ratio with the second valid data ratio.

12 . The memory system according to claim 7 , wherein
the plurality of logical sub-blocks includes a plurality of first logical sub-blocks each set to a first storage mode, and the memory controller is further configured to:
determine the number of logical sub-blocks in which valid data is not stored among the plurality of first logical sub-blocks; and
in respons

Assignees

• Kioxia Corp

Inventors

• Kawaguchi Yuki
• Kojima Yoshihisa
• Amaki Takehiko
• Igahara Shunichi
• Hida Toshikatsu

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title