Semiconductor device including air gap

Patent metadata

Field	Value
Publication number	US-2026075868-A1
Application number	US-202519390051-A
Country	US
Kind code	A1
Filing date	Nov 14, 2025
Priority date	Oct 15, 2021
Publication date	Mar 12, 2026
Grant date	—

Abstract

A semiconductor device of the disclosure includes an active pattern extending on a substrate in a first direction, a gate structure extending on the active pattern in a second direction intersecting the first direction, a source/drain region disposed on at least one side of the gate structure, a source/drain contact connected to the source/drain region, and a contact insulating layer disposed on the source/drain contact. The contact insulating layer includes at least one air gap. The air gap is disposed on an upper surface of the source/drain contact.

First claim

What is claimed is:

1 . A manufacturing method of a semiconductor device, the manufacturing method comprising:
forming an active pattern extending in a first direction in a substrate; forming first and second sacrificial gate structures extending in a second direction intersecting the first direction and spaced apart from each other in the first direction in the substrate, and forming gate spacers on sidewalls of each of the first and second sacrificial gate structures; forming source/drain regions by recessing portions of the active pattern exposed on both sides of the first and second sacrificial gate structures and the gate spacers; forming an interlayer insulating layer covering the gate spacers and the source/drain regions; removing the first and second sacrificial gate structures; forming first and second gate structures respectively including a gate insulating layer on inner sidewalls of the gate spacers and a gate electrode on the gate insulating layer; forming a first sacrificial interlayer insulating layer over the interlayer insulating layer and the first and second gate structures; forming first, second, and third contact structures spaced apart from each other in the first direction and penetrating the interlayer insulating layer and the first sacrificial interlayer insulating layer to contact the respective source/drain regions; forming a second sacrificial interlayer insulating layer over the first sacrificial interlayer insulating layer and the first, second, and third contact structures; forming a mask pattern on the second sacrificial interlayer insulating layer, the mask pattern having an opening overlapping the first and second gate structures and the second contact structure in a vertical direction; forming a recess region by etching the first and second sacrificial interlayer insulating layers using the mask pattern to expose portions of sidewalls of the second contact structure and sidewalls of the first and second gate structures adjacent thereto; and forming a contact insulating layer in the recess region.

2 . The manufacturing method of claim 1 , wherein the mask pattern overlaps the first and third contact structures in the vertical direction.

3 . The manufacturing method of claim 1 , wherein forming each of the first and second gate structures comprises:
forming an insulating layer over a gate insulating layer, a gate electrode, and an interlayer insulating layer; and removing the insulating layer such that an upper surface of the interlayer insulating layer is exposed so as to form a gate capping layer.

4 . The manufacturing method of claim 3 , wherein an upper surface of the gate capping layer is coplanar with an upper surface of the contact insulating layer.

5 . The manufacturing method of claim 1 , wherein forming the first, second, and third contact structures comprises:
forming contact holes penetrating the interlayer insulating layer and the first sacrificial interlayer insulating layer to expose the source/drain regions; and sequentially forming a barrier layer and an embedded conductive layer in each of the contact holes.

6 . The manufacturing method of claim 1 , wherein forming the contact insulating layer comprises:
forming a preliminary contact insulating layer covering the mask pattern; and removing the preliminary contact insulating layer such that upper surfaces of the first and second gate structures are exposed.

7 . The manufacturing method of claim 1 , further comprising removing the first and second sacrificial interlayer insulating layers to expose upper surfaces of the first and second gate structures, upper surfaces of the first and third contact structures, and an upper surface of the contact insulating layer.

8 . The manufacturing method of claim 7 , further comprising:
forming an upper interlayer insulating layer over the first and second gate structures, the first and third contact structures, and the contact insulating layer; and forming a wiring structure penetrating the upper interlayer insulating layer to be connected to the first contact structure, wherein the second contact structure vertically overlaps the upper interlayer insulating layer.

9 . The manufacturing method of claim 1 , wherein an upper surface of the contact insulating layer is coplanar with upper surfaces of the first and third contact structures.

10 . The manufacturing method of claim 1 , wherein the mask pattern overlaps the first and third contact structures in the vertical direction.

11 . The manufacturing method of claim 1 ,
wherein the recess region comprises an upper region exposing the first and second sacrificial interlayer insulating layers and a lower region extending from the upper region to expose portions of sidewalls of the second contact structure and portions of sidewalls of the first and second gate structures, and wherein a width of the upper region in the first direction is greater than a width of the lower region in the first direction.

12 . The manufacturing method of claim 1 , wherein the contact insulating layer comprises at least one air gap.

13 . A manufacturing method of a semiconductor device, the manufacturing method comprising:
forming an active pattern extending in a first direction in a substrate; forming first and second sacrificial gate structures extending in a second direction intersecting the first direction and spaced apart from each other in the first direction in the substrate, and forming gate spacers on sidewalls of each of the first and second sacrificial gate structures; forming a source/drain region by recessing the active pattern exposed on both sides of the gate spacers between the first and second sacrificial gate structures; forming an interlayer insulating layer covering the gate spacers and the source/drain region; removing the first and second sacrificial gate structures and forming first and second gate structures respectively including a gate insulating layer, a gate electrode on the gate insulating layer, and a gate capping layer on the gate spacers, the gate insulating layer, and the gate electrode; forming a first sacrificial interlayer insulating layer over the interlayer insulating layer and the first and second gate structures; forming a preliminary contact structure penetrating the interlayer insulating layer and the first sacrificial interlayer insulating layer to contact the source/drain region; etching the preliminary contact structure in a vertical direction to form a contact structure having an upper surface at a level lower than the first and second gate structures; and forming a contact insulating layer contacting portions of sidewalls of the first and second gate structures exposed from the contact structure.

14 . The manufacturing method of claim 13 , further comprising:
removing the first sacrificial interlayer insulating layer such that upper surfaces of the first and second gate structures are exposed; and forming an upper interlayer insulating layer over the first and second gate structures and the contact insulating layer.

15 . The manufacturing method of claim 14 ,
wherein the interlayer insulating layer further comprises an air gap being in contact with the upper interlayer insulating layer.

16 . The manufacturing method of claim 13 ,
wherein the contact structure includes a barrier layer and an embedded conductive layer on the barrier layer, and wherein an upper surface of the embedded conductive layer is curved.

17 . The manufacturing method of claim 13 , further comprising forming a gate

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Sooyeon
• Bae Deokhan
• Park Juhun
• Lee Yuri
• Jung Yoonyoung

Classifications

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/118

  Nanostructure semiconductor bodies · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title