Package substrate

Patent metadata

Field	Value
Publication number	US-2026068714-A1
Application number	US-202519072390-A
Country	US
Kind code	A1
Filing date	Mar 6, 2025
Priority date	Aug 29, 2024
Publication date	Mar 5, 2026
Grant date	—

Abstract

A package substrate includes: a build-up structure; and a core layer disposed on the build-up structure, wherein the build-up structure includes: a signal ball pad; an interconnection member disposed on the signal ball pad; a signal connection pad disposed on the interconnection member; and a plurality of signal vias and a plurality of signal lines alternately arranged in a vertical direction on the signal connection pad, wherein the interconnection member has a first height in the vertical direction, wherein each of the plurality of signal vias has a second height in the vertical direction, and wherein the first height is greater than the second height.

First claim

What is claimed is:

1 . A package substrate comprising:
a build-up structure; and a core layer disposed on the build-up structure, wherein the build-up structure includes: a signal ball pad; an interconnection member disposed on the signal ball pad; a signal connection pad disposed on the interconnection member; and a plurality of signal vias and a plurality of signal lines alternately arranged in a vertical direction on the signal connection pad, wherein the interconnection member has a first height in the vertical direction, wherein each of the plurality of signal vias has a second height in the vertical direction, and wherein the first height is greater than the second height.

2 . The package substrate of claim 1 , wherein:
the first height ranges from about 200 μm to about 300 μm.

3 . The package substrate of claim 1 , wherein:
the second height ranges from about 5 μm to about 50 μm.

4 . The package substrate of claim 1 , wherein:
the signal ball pad has a first width in a horizontal direction that intersects the vertical direction, wherein the signal connection pad has a second width in the horizontal direction, and wherein the first width is larger than the second width.

5 . The package substrate of claim 1 , wherein:
the signal connection pad has a width ranging from about 100 μm to about 300 μm in a horizontal direction that intersects the vertical direction.

6 . The package substrate of claim 1 , wherein:
the interconnection member has a width ranging from about 20 μm to about 200 μm in a horizontal direction that intersects the vertical direction.

7 . The package substrate of claim 1 , wherein:
the signal ball pad has a width ranging from about 400 μm to about 800 μm in a horizontal direction that intersects the vertical direction.

8 . The package substrate of claim 1 , wherein:
the interconnection member includes a conductive post.

9 . A package substrate comprising:
a build-up structure; and a core layer disposed on the build-up structure, wherein the build-up structure includes: a signal ball pad; a ground ball pad disposed adjacent to the signal ball pad; a signal connection pad spaced apart from the signal ball pad in a first direction by a first interval; a first conductive plane spaced apart from the ground ball pad in the first direction by the first interval and arranged adjacent to the signal connection pad; a signal line spaced apart from the signal connection pad in the first direction by a second interval; and a second conductive plane spaced apart from the first conductive plane in the first direction by the second interval and arranged adjacent to the signal line, wherein the first interval is larger than the second interval.

10 . The package substrate of claim 9 , wherein:
the first interval ranges from about 200 μm to about 300 μm.

11 . The package substrate of claim 9 , wherein:
the second interval ranges from about 5 μm to about 50 μm.

12 . The package substrate of claim 9 , wherein:
the first conductive plane includes a ground plane.

13 . The package substrate of claim 9 , wherein:
the second conductive plane includes an electric power plane.

14 . The package substrate of claim 9 , wherein:
the first conductive plane includes a first opening, and the signal connection pad is disposed within the first opening, the second conductive plane includes a second opening, and the signal line is disposed within the second opening, and an outline of the first opening matches an outline of the second opening.

15 . The package substrate of claim 9 , wherein:
the signal connection pad does not overlap the second conductive plane.

16 . A package substrate comprising:
a first build-up structure; a core layer disposed on the first build-up structure; and a second build-up structure disposed on the core layer, wherein the first build-up structure includes: a signal ball pad; a ground ball pad disposed adjacent to the signal ball pad; a signal interconnection member disposed on the signal ball pad; a ground interconnection member disposed on the ground ball pad and disposed adjacent to the signal interconnection member; a signal connection pad disposed on the signal interconnection member; a plurality of ground planes and a plurality of ground vias alternately arranged in a vertical direction on the ground interconnection member; and a plurality of signal vias and a plurality of signal lines alternately arranged in the vertical direction on the signal connection pad, wherein the signal interconnection member and the ground interconnection member have a first height, wherein each of the plurality of signal vias and each of the plurality of ground vias has a second height, and the first height is greater than the second height.

17 . The package substrate of claim 16 , wherein:
the first build-up structure further includes: a first dielectric material layer covering the signal interconnection member and the ground interconnection member; and a second dielectric material layer covering the signal connection pad, the plurality of signal vias, the plurality of signal lines, the plurality of ground planes, and the plurality of ground vias.

18 . The package substrate of claim 16 , wherein:
the core layer includes a core and a plurality of core through vias, wherein the plurality of core through vias includes: a plurality of signal core through vias connected to the plurality of signal lines; and a plurality of ground core through vias connected to the plurality of ground planes.

19 . The package substrate of claim 16 , wherein:
the plurality of signal lines does not overlap the plurality of ground planes.

20 . The package substrate of claim 19 , wherein:
the signal ball pad overlaps the plurality of ground planes.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yong Seokbeom
• Kim Juwon
• Ahn Sungoh

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title

• H01L23/49838 Primary

  Electricity · mapped topic