Multi-layer electronic device package

Patent metadata

Field	Value
Publication number	US-2026068709-A1
Application number	US-202418818573-A
Country	US
Kind code	A1
Filing date	Aug 28, 2024
Priority date	Aug 28, 2024
Publication date	Mar 5, 2026
Grant date	—

Abstract

An electronic device includes a die, a ground die attach pad, and a power supply die attach pad. Wire bonds connect ground nets from the die to the ground die attach pad. Additional wire bonds connect power supply nets from the die to the power supply die attach pad.Additional wire bonds connect signal nets from the die to pins on a periphery of the electronic device.

First claim

What is claimed is:

1 . An electronic device comprising:
a die; a ground die attach pad; a power supply die attach pad; and wire bonds connecting ground nets from the die to the ground die attach pad, connecting power supply nets from the die to the power supply die attach pad, and connecting signal nets from the die to pins on a periphery of the electronic device.

2 . The electronic device of claim 1 , wherein the ground die attach pad and the power supply die attach pad are on a first plane in a first layer.

3 . The electronic device of claim 2 , wherein the power supply die attach pad comprises L-shaped bars that extend around a periphery of the first layer and substantially surround the ground die attach pad.

4 . The electronic device of claim 2 further comprising a second layer comprising a first ground pad and a first power supply pad, wherein the first ground pad and the first power supply pad are on a second plane.

5 . The electronic device of claim 4 further comprising a via layer disposed between the first layer and the second layer, the via layer including vias that electrically connect the ground die attach pad to the first ground pad and vias that electrically connect the power supply die attach pad to the first power supply pad.

6 . The electronic device of claim 5 further comprising second ground pad disposed on a bottom of the first ground pad and a second power supply pad disposed on the first power supply pad, wherein the second ground pad and the second power supply pad are on a third plane.

7 . The electronic device of claim 6 , wherein the first ground pad and the first power supply pad have x-y dimensions that are larger than x-y dimensions of the second ground pad and the second power supply pad respectively.

8 . An electronic device comprising:
a first layer having at least two die attach pads; a second layer having at least two first electrical pads, the at least two first electrical pads substantially aligned with the at least two die attach pads; a third layer having at least two second electrical pads, the at least two second electrical pads substantially aligned with the at least two first electrical pads; a die disposed on the first layer; and wire bonds connecting power nets from the die to the at least two die attach pads and connecting signal nets from the die to pins on a periphery of the electronic device.

9 . The electronic device of claim 8 further comprising a via layer having vias connecting the at least two die attach pads of the first layer with the at least two first electrical pads of the second layer.

10 . The electronic device of claim 9 , wherein the at least two die attach pads comprises a ground die attach pad and a power supply die attach pad, wherein the ground die attach pad and the power die attach pad are on a first plane.

11 . The electronic device of claim 10 , where the at least two first electrical pads comprises a first ground pad substantially aligned with the ground die attach pad and a first power supply pad substantially aligned with the power supply die attach pad, wherein the first ground pad and the first power supply pad are on a second plane.

12 . The electronic device of claim 11 , where the at least two second electrical pads comprises a second ground pad substantially aligned with the first ground pad and a second power supply pad substantially aligned with the first power supply pad, wherein the second ground pad and the second power supply pad are on a third plane.

13 . The electronic device of claim 12 , wherein the ground die attach pad and the power supply die attach pad are physically separated by a first gap, wherein the first ground pad and the first power supply pad are physically separated by a second gap, and wherein the second ground pad and the second power supply pad are physically separated by a third gap.

14 . The electronic device of claim 10 , wherein the power supply die attach pad comprises L-shaped bars that extend around a periphery of the first layer and substantially surround the ground die attach pad.

15 . The electronic device of claim 10 , wherein the wire bonds comprise a first set of wire bonds connecting ground nets from the die to the ground die attach pad, a second set of wire bonds connecting power supply nets from the die to the power supply die attach pad, and a third set of wire bonds connecting the signal nets from the die to the pins.

16 . A method comprising:
forming a first plated layer in a surface of a substrate; forming a second plated layer in an opposite surface of the substrate, the first plated layer electrically connected to the second plated layer via a via layer, wherein inner walls of vias in the via layer are plated; forming a third plated layer on the second plated layer; connecting wire bonds from a die disposed on the first plated layer to the first plated layer; and forming a mold compound over the die and wire bonds.

17 . The method of claim 16 , wherein forming the first plated layer includes forming a ground die attach pad via electroplating and forming a power supply die attach pad via electroplating, wherein the ground die attach pad and the power supply die attach pad are on a first plane and physically separated by a first gap.

18 . The method of claim 17 , wherein forming a second plated layer includes forming a first ground pad and a first power supply pad via electroplating, wherein the first ground pad and the first power supply pad are on a second plane and physically separated by a second gap.

19 . The method of claim 18 , wherein forming a third plated layer includes forming a second ground pad and a second power supply pad via electroplating, wherein the second ground pad and the second power supply pad are on a third plane and physically separated by a third gap.

20 . The method of claim 17 , wherein connecting wire bonds from a die disposed on the first plated layer to the first plated layer includes connecting a first set of wire bonds from ground nets on the die to the ground die attach pad, connecting a second set of wire bonds from power supply nets on the die to the power supply die attach pad, and connecting a third set of wire bonds from signal nets on the die to pins on a periphery of the substrate.

Assignees

• Texas Instruments Inc

Inventors

• Ankamah-Kusi Sylvester
• O'Connor Shawn
• Esquejo Jovenic
• Travis Blake
• Bakshi Harshpreet Singh Phull
• Murugan Rajen Manicon
• Khan Muhammad

Classifications

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/05 Primary

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title