Clock data recovery linearity improvement

Patent metadata

Field	Value
Publication number	US-2026066908-A1
Application number	US-202418818004-A
Country	US
Kind code	A1
Filing date	Aug 28, 2024
Priority date	Aug 28, 2024
Publication date	Mar 5, 2026
Grant date	—

Abstract

A method for phase adjustment includes receiving a phase control signal for a phase interpolator, determining the phase control signal is located within one of first phase zones, and adjusting the phase control signal by a first step size upon determining the phase control signal is located within one of the first phase zones. The method also includes determining the phase control signal is located within one of second phase zones, and adjusting the phase control signal by a second step size larger than the first step size upon determining the phase control signal is located within one of the second phase zones.

First claim

What is claimed is:

1 . A system, comprising:
a phase control circuit having an input and an output, wherein the phase control circuit is configured to output a phase control signal at the output of the phase control circuit; a phase interpolator coupled to the output of the phase control circuit; and a step-size selection circuit configured to receive a first phase adjustment signal having a first step size, a second phase adjustment signal having a second step size larger than the first step size, and the phase control signal, and wherein the step-size selection circuit is configured to:
output the first phase adjustment signal to the input of the phase control circuit if the phase control signal is located within one of first phase zones; and
output the second phase adjustment signal to the input of the phase control circuit if the phase control signal is located within one of second phase zones.

2 . The system of claim 1 , wherein the first phase zones include clock-switching boundaries of the phase interpolator.

3 . The system of claim 2 , wherein the phase interpolator is configured to receive clock signals, and the phase interpolator is configured to:
select a pair of the clock signals at a time based on the phase control signal; perform phase interpolation on the selected pair of the clock signals; and switch the pair of the clock signals that is selected when the phase control signal crosses one of the clock-switching boundaries.

4 . The system of claim 3 , wherein the clock signals are evenly spaced apart in phase.

5 . The system of claim 4 , wherein the clock signals are spaced apart by 90 degrees.

6 . The system of claim 1 , wherein the first phase zones include weight-transition boundaries of the phase interpolator.

7 . The system of claim 1 , wherein the step-size selection circuit comprises:
a multiplexer having a first input, a second input, a select input, and an output, wherein the first input of the multiplexer is configured to receive the first phase adjustment signal, the second input of the multiplexer is configured to receive the second phase adjustment signal, and the output of the multiplexer is coupled to the input of the phase control circuit; and a compare circuit having an input and an output, wherein the input of the compare circuit is coupled to the output of the phase control circuit, and the output of compare circuit is coupled to the select input of the multiplexer.

8 . The system of claim 7 , wherein the compare circuit is configured to:
compare the phase control signal with the first phase zones; and cause the multiplexer to select one of the first phase adjustment signal and the second phase adjustment signal based on the comparison.

9 . The system of claim 8 , wherein the phase control signal comprises a phase control code, the first phase zones includes codes for the phase control code, and the compare circuit is configured to cause the multiplexer to select the first phase adjustment signal if the phase control code matches one of the codes in the first phase zones.

10 . The system of claim 9 , wherein the compare circuit is configured to cause the multiplexer to select the second phase adjustment signal if the phase control code does not match any of the codes in the first phase zones.

11 . The system of claim 7 , wherein the first phase zones include clock-switching boundaries of the phase interpolator.

12 . The system of claim 7 , wherein the first phase zones include weight-transition boundaries of the phase interpolator.

13 . The system of claim 1 , wherein the phase control circuit is configured to update the phase control signal based on the first phase adjustment signal or the second phase adjustment signal output by the step-size selection circuit.

14 . The system of claim 1 , further comprising a data sampler coupled to the phase interpolator, wherein the phase interpolator is configured to output a sampling clock signal to the data sampler, and set a phase of the sampling clock based on the phase control signal.

15 . The system of claim 14 , wherein the data sampler is configured to receive a serial data signal, and sample the serial data signal on edges of the sampling clock signal to generate data samples.

16 . The system of claim 15 , further comprising a phase adjuster coupled to the data sampler, wherein the phase adjuster is configured to generate the first phase adjustment signal and the second phase adjustment signal based on the data samples.

17 . A method for adjusting a phase of a clock signal, comprising:
receiving a phase control signal for a phase interpolator; determining the phase control signal is located within one of first phase zones; adjusting the phase control signal by a first step size upon determining the phase control signal is located within one of the first phase zones; determining the phase control signal is located within one of second phase zones; and adjusting the phase control signal by a second step size larger than the first step size upon determining the phase control signal is located within one of the second phase zones.

18 . The method of claim 17 , wherein the first phase zones include clock-switching boundaries of the phase interpolator.

19 . The method of claim 18 , further comprising:
receiving clock signals; selecting a pair of the clock signals at a time based on the phase control signal; performing phase interpolation on the selected pair of clock signals using the phase interpolator; and switching the pair of the clock signals that is selected when the phase control signal crosses one of the clock-switching boundaries.

20 . The method of claim 19 , wherein the clock signals are evenly spaced apart in phase.

Assignees

• Qualcomm Inc

Inventors

• Chang Chia Heng
• Zhu Zhi
• Deans Russell

Classifications

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/089

  the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence) · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title