Storage system including storage device and host device

Patent metadata

Field	Value
Publication number	US-2026066000-A1
Application number	US-202519260981-A
Country	US
Kind code	A1
Filing date	Jul 7, 2025
Priority date	Aug 27, 2024
Publication date	Mar 5, 2026
Grant date	—

Abstract

Provided is an operating method of a storage device, the operating method including providing mapping information to a host when an initialization operation is performed, the mapping information including information about a plurality of data transmission rates and voltage levels of a first voltage, receiving the first voltage from the host through a first voltage pin, the first voltage having a first voltage level, receiving a first change request from the host, the first change request being a request to change a data transmission rate from a first data transmission rate to a second data transmission rate, and receiving the first voltage from the host through the first voltage pin, the first voltage having a second voltage level mapped to the second data transmission rate.

First claim

1 . An operating method of a storage device, the operating method comprising:
providing mapping information to a host when an initialization operation is performed, the mapping information including information about a plurality of data transmission rates and voltage levels of a first voltage; receiving the first voltage from the host through a first voltage pin, the first voltage having a first voltage level; receiving a first change request from the host, the first change request being a request to change a data transmission rate from a first data transmission rate to a second data transmission rate; and receiving the first voltage from the host through the first voltage pin, the first voltage having a second voltage level mapped to the second data transmission rate.

2 . The operating method of claim 1 , wherein the second data transmission rate is slower than the first data transmission rate, and the second voltage level is lower than the first voltage level.

3 . The operating method of claim 1 , wherein the second data transmission rate is faster than the first data transmission rate, and the second voltage level is higher than the first voltage level.

4 . The operating method of claim 1 , further comprising:
transmitting a response to the first change request to the host, wherein the receiving of the first voltage having the second voltage level through the first voltage pin is performed after the response to the first change request is transmitted to the host.

5 . The operating method of claim 1 , wherein the receiving of the first change request to change the data transmission rate from the first data transmission rate to the second data transmission rate is performed after the receiving of the first voltage having the second voltage level through the first voltage pin.

6 . The operating method of claim 1 , further comprising:
receiving a second voltage through a second voltage pin when the initialization operation is performed; generating a regulated voltage by regulating the second voltage; driving an internal circuit by using the regulated voltage as a driving voltage; and switching the driving voltage from the regulated voltage to the first voltage received through the first voltage pin after the initialization operation is performed.

7 . (canceled)

8 . The operating method of claim 1 , further comprising:
providing a line-reset signal to the host through a line connected to the host when the initialization operation is performed, wherein a length of the line-reset signal represents the first voltage level.

9 . The operating method of claim 1 , further comprising:
providing data to the host based on the first data transmission rate after the initialization operation is performed, wherein the mapping information about voltage levels corresponding to the plurality of data transmission rates includes mapping information about the first data transmission rate and the first voltage level.

10 . A storage device comprising:
a non-volatile memory; an interconnect circuit connected to a host through an input/output pin; a first pin configured to receive a first voltage; and a device controller configured to:
control an operation of the non-volatile memory based on a command received through the input/output pin,
provide mapping information about data transmission rates and voltage levels to the host through the input/output pin, and
drive the interconnect circuit based on a first voltage having a voltage level mapped to a data transmission rate about the input/output pin.

11 . (canceled)

12 . The storage device of claim 10 , wherein the interconnect circuit is configured to receive a data transmission rate change request to change a data transmission rate from a first data transmission rate to a second data transmission rate when a data transmission rate change operation is performed, and a voltage level of the first voltage received through the first pin is changed from a first voltage level mapped to the first data transmission rate to a second voltage level mapped to the second data transmission rate.

13 . The storage device of claim 12 , wherein the second data transmission rate is faster than the first data transmission rate, and the second voltage level is higher than the first voltage level.

14 . The storage device of claim 12 , wherein the voltage level of the first voltage is changed to the second voltage level before the interconnect circuit receives the data transmission rate change request.

15 . The storage device of claim 12 , wherein the second data transmission rate is slower than the first data transmission rate, and the second voltage level is lower than the first voltage level.

16 . The storage device of claim 12 , wherein the voltage level of the first voltage is changed to the second voltage level after the interconnect circuit transmits a data transmission rate change response to the host, the data transmission rate change response corresponding to the data transmission rate change request.

17 . A storage system comprising:
a storage device configured to drive an internal circuit based on a first voltage and output mapping information about a plurality of data transmission rates and voltage levels of the first voltage; and a host device configured to
transmit/receive data to/from the storage device based on a first data transmission rate,
obtain a first voltage level mapped to the first data transmission rate based on the mapping information, and
provide the first voltage having the first voltage level to the storage device.

18 . The storage system of claim 17 , wherein
the host device is configured to provide, to the storage device, a data transmission rate change request to change a data transmission rate from the first data transmission rate to a second data transmission rate, the storage device is configured to provide, to the host device, a data transmission rate change response corresponding to the data transmission rate change request, and the host device is configured to change a voltage level of the first voltage from the first voltage level to a second voltage level based on the mapping information.

19 . The storage system of claim 18 , wherein the second data transmission rate is less than or equal to the first data transmission rate, and the second voltage level is less than or equal to the first voltage level.

20 . The storage system of claim 18 , wherein the second data transmission rate is greater than or equal to the first data transmission rate, and the second voltage level is greater than or equal to the first voltage level.

21 . The storage system of claim 18 , wherein the host device is configured to change the voltage level of the first voltage to the second voltage level before the data transmission rate change request is provided to the storage device.

22 . The storage system of claim 18 , wherein the host device is configured to change the voltage level of the first voltage to the second voltage level after the data transmission rate change response is received from the storage device.

23 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jungsik
• Seo Sungho
• Cho Yongwon
• Choe Gyuseok

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G11C16/20 Primary

  Initialising; Data preset; Chip identification · CPC title