Method and system for shifting data within memory

Patent metadata

Field	Value
Publication number	US-2026056895-A1
Application number	US-202519373455-A
Country	US
Kind code	A1
Filing date	Oct 29, 2025
Priority date	Apr 29, 2024
Publication date	Feb 26, 2026
Grant date	—

Abstract

Provided is a method for shifting data within a memory, which is performed by a direct memory access (DMA) controller, and which includes receiving a task associated with an operation of shifting target data stored in a first area of a memory connected to the DMA controller to a second area of the memory, receiving the target data from the memory, determining a priority of each of a plurality of data items divided from the target data based on an address of the first area and an address of the second area, generating a plurality of write requests corresponding to the plurality of data items, and transmitting the plurality of generated write requests sequentially to a memory controller associated with the memory, so that the plurality of data items are stored in the second area in sequence according to the determined priority.

First claim

1 . A method for shifting data within a memory, the method being performed by a direct memory access (DMA) controller and comprising:
receiving a task associated with an operation of shifting target data stored in a first area of a memory connected to the DMA controller to a second area of the memory; receiving the target data from the memory; determining, based on an address of the first area and an address of the second area, a priority of each of a plurality of data items divided from the target data; generating a plurality of write requests corresponding to the plurality of data items; and transmitting the plurality of write requests sequentially to a memory controller associated with the memory, so that the plurality of data items are stored in the second area in sequence according to the determined priority.

2 . The method according to claim 1 , wherein the memory controller is configured to sequentially store in the second area, in response to sequentially receiving the plurality of write requests from the DMA controller, the plurality of data items corresponding to the plurality of write requests.

3 . The method according to claim 1 , wherein the generating the plurality of write requests comprises sequentially generating the plurality of write requests according to the determined priority.

4 . The method according to claim 3 , wherein
the plurality of data items comprises a first data item and a second data item with a lower priority than the first data item,
the plurality of write requests comprise a first write request corresponding to the first data item and a second write request corresponding to the second data item, and
the generating the plurality of write requests comprises:
withholding, in response to receiving the second data item before receiving the first data item, generation of the second write request; and
generating, in response to transmitting all write requests associated with data items having higher priorities than the first data item to the memory controller and to receiving the first data item, the first write request.

5 . The method according to claim 1 , wherein the determining the priority comprises, in response to at least a portion of the first area and at least a portion of the second area overlapping with each other, determining the priority.

6 . The method according to claim 1 , wherein
each of the plurality of data items is stored in each of a plurality of sub-areas in the first area, and
the determining the priority comprises, assigning, in response to an address of the second area being higher than an address of the first area, a higher priority to a data item stored in a sub-area of a higher address of the plurality of sub-areas.

7 . The method according to claim 1 , wherein
each of the plurality of data items is stored in each of a plurality of sub-areas in the first area, and
the determining the priority comprises, assigning, in response to an address of the second area being lower than an address of the first area, a higher priority to a data item stored in a sub-area of a lower address of the plurality of sub-areas.

8 . The method according to claim 1 , wherein
the generating the plurality of write requests comprises calculating address information of a plurality of sub-areas in the second area where the plurality of data items are to be stored, and
each of the plurality of write requests comprises address information of each of the plurality of sub-areas.

9 . The method according to claim 1 , wherein
the transmitting the plurality of write requests comprises transmitting, in response to a first condition or a second condition being satisfied, each of the plurality of write requests to the memory controller,
the first condition is that a read of an area where a data item corresponding to each of the plurality of write requests is to be stored is completed, and
the second condition is that the area where the data item corresponding to each of the plurality of write requests is to be stored does not overlap with the first area.

10 . The method according to claim 1 , wherein
the receiving the target data comprises:
generating a plurality of read requests associated with the plurality of data items;
transmitting the plurality of generated read requests to the memory controller; and
receiving the plurality of data items corresponding to the plurality of read requests from the memory controller.

11 . The method according to claim 10 , wherein
the transmitting the plurality of read requests comprises sequentially transmitting the plurality of generated read requests to the memory controller, so that the plurality of data items are read from the first area according to the determined priority, and
the receiving the plurality of data items comprises receiving the plurality of data items in sequence according to the determined priority.

12 . The method according to claim 10 , wherein the receiving the plurality of data items comprises receiving the plurality of data items in sequence independent of the priority of each of the plurality of data items.

13 . The method according to claim 10 , wherein the generating the plurality of read requests comprises generating the plurality of read requests in sequence according to the determined priority.

14 . The method according to claim 10 , wherein
the generating the plurality of read requests comprises calculating address information of a plurality of sub-areas in the first area where the plurality of data items are stored, and
each of the plurality of read requests comprises address information of each of the plurality of sub-areas.

15 . A memory system, comprising:
a direct memory access (DMA) controller; a memory connected to the DMA controller; and a memory controller associated with the memory, wherein the DMA controller is configured to:
receive a task associated with an operation of shifting a target data stored in a first area of the memory to a second area of the memory;
receive the target data from the memory;
determine, based on an address of the first area and an address of the second area, a priority of each of a plurality of data items divided from the target data;
generate a plurality of write requests corresponding to the plurality of data items; and
transmit the plurality of generated write requests sequentially to the memory controller, so that the plurality of data items are stored in the second area in sequence according to the determined priority.

16 . The memory system according to claim 15 , wherein the memory controller is configured to sequentially store in the second area, in response to sequentially receiving the plurality of write requests from the DMA controller, the plurality of data items corresponding to the plurality of write requests.

17 . The memory system according to claim 15 , wherein the DMA controller is configured to, in response to at least a portion of the first area and at least a portion of the second area overlapping with each other, determine the priority.

18 . The memory system according to claim 15 , wherein
each of the plurality of data items is stored in each of a plurality of sub-areas in the first area, and
the DMA controller is configured to assign, in response to an address of the second area being higher than an address of the first area, a higher priority to a data item stored in a sub-area of a higher address of the plurality of sub-

Assignees

• Rebellions Inc

Inventors

• Kim Hyunho
• Je Sangeun
• Bae Jaewan

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2213/28

  DMA · CPC title