Transition metal containing contact with reduced contact resistivity

US2026052752A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2026052752-A1
Application numberUS-202418807152-A
CountryUS
Kind codeA1
Filing dateAug 16, 2024
Priority dateAug 16, 2024
Publication dateFeb 19, 2026
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a non-magnetic transition-metal doped contact silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The non-magnetic transition-metal doped contact silicide layer includes a non-magnetic transition-metal, a first metal, and a silicon containing compound, and includes greater than or about 8.0 E+13 per cm 2 non-magnetic transition-metal atoms. The first metal layer includes the first metal and overlies the non-magnetic transition-metal doped contact silicide layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device, comprising: a substrate, an oxide disposed on the substrate defining one or more features; and a silicide contact disposed on the substrate in the one or more features, the silicide contact comprising: a non-magnetic transition-metal, and at least a first metal. 2 . The semiconductor device of claim 1 , wherein the contact exhibits a Schottky Barrier Height that is at least about 5% less than a Schottky Barrier Height in a semiconductor device that does not contain a non-magnetic transition-metal in the silicide contact. 3 . The semiconductor device of claim 1 , wherein the contact exhibits a Schottky Barrier Height of less than 1.0 eV. 4 . The semiconductor device of claim 1 , wherein the silicide comprises a concentration of the non-magnetic transition-metal of greater than or about 8 E+13 per cm 2 . 5 . The semiconductor device of claim 4 , wherein the non-magnetic transition-metal comprises yttrium, scandium, zirconium, or a combination thereof. 6 . The semiconductor device of claim 1 , wherein the first metal comprises titanium, zirconium, nickel, molybdenum, gold, tungsten, palladium, platinum, chromium, or a combination thereof. 7 . The semiconductor device of claim 6 , wherein the non-magnetic transition-metal is yttrium, and the first metal is titanium. 8 . The semiconductor device of claim 4 , wherein the silicide contact comprises a concentration of the non-magnetic transition-metal of greater than or about 1 E+14 per cm 2 . 9 . The semiconductor device of claim 1 , wherein the non-magnetic transition-metal is disposed in a n-MOS region. 10 . The semiconductor device of claim 1 , wherein non-magnetic transition-metal is disposed in a p-MOS region. 11 . A semiconductor device, comprising: a silicon-containing substrate; a silicon oxide disposed on the substrate defining one or more features; and a silicide contact disposed on the substrate in the one or more features, the silicide contact comprising: a non-magnetic transition-metal, and at least a first metal. 12 . The semiconductor device of claim 11 , wherein the first metal is molybdenum, titanium, zirconium, nickel, or a combination thereof. 13 . The semiconductor device of claim 12 , wherein the non-magnetic transition-metal is zirconium, yttrium, scandium, or a combination thereof. 14 . A method of forming a semiconductor device, comprising: depositing a non-magnetic transition-metal layer comprising a non-magnetic transition-metal over a silicon containing substrate in at least a first feature; depositing a first metal layer comprising a first metal over the non-magnetic transition-metal layer; and annealing the semiconductor device, forming a silicide contact positioned between the first metal layer and the silicon containing substrate, the silicide contact comprising the first metal and the non-magnetic transition-metal. 15 . The method of claim 14 , wherein depositing the non-magnetic transition-metal layer includes exposing the silicon containing substrate in the at least the first feature to a non-magnetic transition-metal precursor. 16 . The method of claim 15 , wherein depositing the first metal layer includes exposing the non-magnetic transition-metal layer to a first metal precursor. 17 . The method of claim 16 , wherein the non-magnetic transition-metal comprises yttrium, zirconium, scandium, or a combination thereof. 18 . The method of claim 14 , wherein the contact exhibits a Schottky Barrier Height that is at least about 5% less than a Schottky Barrier Height in a contact that does not contain a non-magnetic transition-metal. 19 . The method of claim 14 , wherein the silicide contact comprises a non-magnetic transition-metal concentration of greater than or about 8 E+13 per cm 2 . 20 . The method of claim 14 , wherein the silicide contact comprises a concentration of the non-magnetic transition-metal of greater than or about 1 E+14 per cm 2 .

Assignees

Inventors

Classifications

  • being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

  • Electrodes ohmically coupled to a semiconductor · CPC title

  • H10W20/066Primary

    by forming silicides of refractory metals · CPC title

  • to diamond, semiconducting diamond-like carbon or graphene · CPC title

  • Schottky drain or source electrodes for IGFETs · CPC title

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What does patent US2026052752A1 cover?
The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a non-magnetic transition-metal doped contact silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The non-magnetic transition-me…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10W20/066. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Feb 19 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).