Semiconductor system including a plurality of dies and method for verifying security between the plurality of dies

Patent metadata

Field	Value
Publication number	US-2026050695-A1
Application number	US-202519196344-A
Country	US
Kind code	A1
Filing date	May 1, 2025
Priority date	Aug 19, 2024
Publication date	Feb 19, 2026
Grant date	—

Abstract

A semiconductor system includes a first die, including a first security processor configured to store a shared key and an application processor, and a second die connected to the first die through a first channel and including a second security processor configured to store the shared key. The application processor may transmit a security request to the first security processor in response to a request for a security-required operation of the second die. The first security processor, in response to the security request, may be configured to generate an authentication code based on the shared key and transmit a security message, including a command corresponding to the security-required operation of the second die and the authentication code, to the second security processor through the first channel. The second security processor may determine whether the security message has been tampered with, using the authentication code and the shared key.

First claim

What is claimed is:

1 . A semiconductor system comprising:
a first die comprising a first security processor and an application processor, the first security processor being configured to store a shared key; and a second die connected to the first die through a first channel and comprising a second security processor configured to store the shared key, wherein the application processor is configured to transmit a security request to the first security processor in response to a request for a security-required operation of the second die, wherein the first security processor is configured to, in response to the security request:
generate an authentication code based on the shared key; and
transmit a security message to the second security processor through the first channel, the security message comprising a command corresponding to the security-required operation of the second die and the authentication code, and
wherein the second security processor is configured to determine that the security message has been tampered with, using the authentication code and the shared key.

2 . The semiconductor system of claim 1 ,
wherein the first security processor comprises a first cryptographic circuit configured to generate the authentication code from the command using the shared key, wherein the second security processor comprises a second cryptographic circuit configured to generate a decoding code from the command transmitted through the security message using the shared key, and wherein the second security processor is configured to determine that the security message has not been tampered with, based on the decoding code matching the authentication code.

3 . The semiconductor system of claim 2 ,
wherein the application processor is configured to transmit a first security request to the first security processor in response to a first operation request for a first operation to set a security level of a first intellectual property (IP) block included in the second die, wherein the first security processor is configured to transmit a first security message to the second security processor in response to the first security request, the first security message comprising a first command corresponding to the first operation, first specific information corresponding to the first IP block, and the authentication code, and wherein the second security processor is configured to:
determine that the first security message has been tampered with, using the authentication code and the shared key, and
based on determining that the first security message has not been tampered with, set the security level of the first IP block to a first security level based on the first command.

4 . The semiconductor system of claim 3 ,
wherein the application processor is configured to transmit a second security request to the first security processor in response to a second operation request for a second operation to generate a security key for the first IP block, wherein the first security processor is configured to transmit a second security message to the second security processor in response to the second security request, the second security message comprising a second command corresponding to the second operation, the first specific information, and the authentication code, and wherein the second security processor is configured to:
determine that the second security message has been tampered with, using the authentication code and the shared key, and
based on determining that the second security message has not been tampered with, generate the security key for the first IP block through the second cryptographic circuit based on the second command.

5 . The semiconductor system of claim 2 ,
wherein the application processor is configured to transmit a third security request and data to the first security processor in response to a third operation request for a third operation to transmit data to a second IP block included in the second die, wherein the first security processor is configured to transmit a third security message to the second security processor in response to the third security request, the third security message comprising a third command corresponding to the third operation, second specific information corresponding to the second IP block, the data, and the authentication code, and wherein the second security processor is configured to:
determine that the third security message has been tampered with, using the authentication code and the shared key, and
based on determining that the third security message has not been tampered with, transmit the data to the second IP block based on the third command.

6 . The semiconductor system of claim 1 ,
wherein the application processor is configured to transmit a fourth security request to the first security processor in response to a fourth operation request for verifying the second die, wherein the first security processor is configured to transmit a fourth security message to the second security processor in response to the fourth security request, the fourth security message comprising a fourth command corresponding to the fourth operation request, an identifier, and the authentication code, and wherein the second security processor is configured to determine that the fourth security message has been tampered with, using the authentication code and the shared key.

7 . The semiconductor system of claim 6 ,
wherein the second security processor is configured to:
generate a reply authentication code using the shared key based on determining that the fourth security message has not been tampered with; and
transmit a reply security message to the first security processor, the reply security message comprising the reply authentication code, security status data of the second die, and a reply identifier corresponding to the identifier, and
wherein the first security processor is configured to:
determine that the reply security message has been tampered with, using the reply authentication code and the shared key, and
determine that the security status data has not been tampered with, based on determining that the reply security message has not been tampered with and the reply identifier matches the identifier.

8 . The semiconductor system of claim 2 ,
wherein the application processor is configured to transmit a fifth security request to the first security processor in response to a drive request for driving a third IP block included in the second die, wherein the first security processor is configured to:
load a boot image for the third IP block from memory device in response to the fifth security request; and
transmit a fifth security message to the second security processor, the fifth security message comprising a fifth command corresponding to the drive request, the boot image, third specific information corresponding to the third IP block, and the authentication code, and
wherein the second security processor is configured to:
determine that the fifth security message has been tampered with, using the authentication code and the shared key, and
based on determining that the fifth security message has not been tampered with, drive the third IP block using the boot image based on the fifth command.

9 . The semiconductor system of claim 8 ,
wherein the first security processor is configured to transmit the fifth security message to the second security processor through a second channel that is different from the first channel, wherein the third IP block comprises a second communication controller connected to a first communication controller of the first die through the first channel, and wherein the second security processor

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Keunyoung
• Lee Eunsung
• Park Dongjin
• Lee Jaeyong

Classifications

• H04L2463/062

  applying encryption of the keys · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title

• H04L63/045

  wherein the sending and receiving network entities apply hybrid encryption, i.e. combination of symmetric and asymmetric encryption (cryptographic mechanisms or cryptographic arrangements using a plurality of keys or algorithms H04L9/14) · CPC title

• H04L63/061

  for key exchange, e.g. in peer-to-peer networks (cryptographic mechanisms or cryptographic arrangements for key agreement H04L9/0838) · CPC title

• H04L63/123 Primary

  received data contents, e.g. message integrity · CPC title