Semiconductor device

Patent metadata

Field	Value
Publication number	US-2026047158-A1
Application number	US-202519014999-A
Country	US
Kind code	A1
Filing date	Jan 9, 2025
Priority date	Aug 12, 2024
Publication date	Feb 12, 2026
Grant date	—

Abstract

A semiconductor device may include a substrate, a first source/drain pattern and a second source/drain pattern spaced apart in a first direction on the substrate, a height from an upper surface of a central portion of the first source/drain pattern to an upper surface of the substrate in a vertical direction is lower than a height from an upper surface of an edge of the first source/drain pattern to the upper surface of the substrate, a plurality of channel patterns connecting between the first source/drain pattern and the second source/drain pattern, and the plurality of channel patterns stacked to be spaced apart from each other, a gate structure surrounding the plurality of channel patterns and extending in a second direction, and a contact plug extending in the vertical direction from an upper surface of the first source/drain pattern, and the contact plug connected to the first source/drain pattern.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate; a first source/drain pattern and second source/drain pattern spaced apart in a first direction on the substrate; a height from an upper surface of a central portion of the first source/drain pattern to an upper surface of the substrate in a vertical direction is lower than a height from an upper surface of an edge of the first source/drain pattern to the upper surface of the substrate in the vertical direction, the vertical direction being a direction perpendicular to the upper surface of the substrate; a plurality of channel patterns connecting between the first source/drain pattern and the second source/drain pattern, and the plurality of channel patterns stacked to be spaced apart from each other; a gate structure surrounding the plurality of channel patterns and extending in a second direction, the second direction crossing the first direction; and a contact plug extending in the vertical direction from an upper surface of the first source/drain pattern, and the contact plug connected to the first source/drain pattern, wherein the first source/drain pattern comprises
a first source/drain layer adjacent to the gate structure,
a second source/drain layer on the first source/drain layer, and
the second source/drain layer comprising first conductivity type impurities, and
a bottom level of the second source/drain layer is lower than a bottom level of the contact plug.

2 . The semiconductor device of claim 1 , further comprising
a third source/drain layer, and the third source/drain layer does not comprise the first conductivity type impurities between the first source/drain layer and the second source/drain layer.

3 . The semiconductor device of claim 2 , wherein
a concentration of germanium (Ge) comprised in at least one among the second source/drain layer or the third source/drain layer is greater than a concentration of germanium (Ge) comprised in the first source/drain layer.

4 . The semiconductor device of claim 1 , wherein
the contact plug further comprises a silicide pattern, and the second source/drain layer surrounds the silicide pattern.

5 . The semiconductor device of claim 1 , wherein the first conductivity type impurities comprise P-type impurities.

6 . The semiconductor device of claim 1 , wherein a cross-section of the first source/drain layer, according to the first direction and the vertical direction, has a concave upper surface.

7 . The semiconductor device of claim 6 , wherein an upper surface of the first source/drain pattern, according to a cross-section view in the first direction and the vertical direction, has a slope that increases and then decreases with respect to an upper surface of the substrate from a central portion in the first direction to an edge in the first direction.

8 . The semiconductor device of claim 6 , wherein an upper surface of the first source/drain pattern, according to a cross-section view in the first direction and the vertical direction, has a slope that increases with respect to an upper surface of the substrate from a central portion in the first direction to an edge in the first direction.

9 . A semiconductor device, comprising:
a substrate comprising a first region and a second region; a first source/drain pattern and a second source/drain pattern spaced apart in a first direction on the first region of the substrate; a height from an upper surface of a central portion of the first source/drain pattern to an upper surface of the substrate in a vertical direction is higher than, or a same height as, a height from an upper surface of an edge of the first source/drain pattern to the upper surface of the substrate in the vertical direction, the vertical direction being a direction perpendicular to the upper surface of the substrate; a plurality of first channel patterns connecting between the first source/drain pattern and the second source/drain pattern, and the plurality of first channel patterns stacked to be spaced apart from each other; a first gate structure surrounding the plurality of first channel patterns and extending in a second direction, the second direction crossing the first direction; a first contact plug extending in the vertical direction,
the first contact plug penetrating an upper surface of the first source/drain pattern by a first depth, the first depth being a distance from an upper surface of the first source/drain pattern to a bottom surface of the first contact plug, and
the first contact plug connected to the first source/drain pattern;
a third source/drain pattern and a fourth source/drain pattern spaced apart in the first direction on the second region of the substrate; a height from an upper surface of a central portion of the third source/drain pattern in the vertical direction is lower than a height from the upper surface of an edge of the third source/drain pattern to the upper surface of the substrate in the vertical direction; a plurality of second channel patterns connecting between the third source/drain pattern and the fourth source/drain pattern, and the plurality of second channel patterns stacked to be spaced apart from each other; a second gate structure surrounding the second channel patterns and extending in the second direction; and a second contact plug extending in the vertical direction,
the second contact plug penetrating from an upper surface of the third source/drain pattern by a second depth, the second depth being a distance from an upper surface of the third source/drain pattern to a bottom surface of the second contact plug, and
the second contact plug connected to the third source/drain pattern,
wherein the second depth is greater than the first depth, the third source/drain pattern comprises
a first source/drain layer adjacent to the second gate structure,
a second source/drain layer on the first source/drain layer, and
the second source/drain layer comprising first conductivity type impurities, and
a bottom level of the second source/drain layer is lower than a bottom level of the second contact plug.

10 . The semiconductor device of claim 9 , further comprising a third source/drain layer that does not comprise the first conductivity type impurities between the first source/drain layer and the second source/drain layer.

11 . The semiconductor device of claim 10 , wherein a concentration of germanium (Ge) comprised in at least one among the second source/drain layer or the third source/drain layer is greater than a concentration of germanium (Ge) comprised in the first source/drain layer.

12 . The semiconductor device of claim 9 , wherein
the second contact plug further comprises a silicide pattern, and the second source/drain layer surrounds the silicide pattern.

13 . The semiconductor device of claim 9 , wherein the first conductivity type impurities comprise P-type impurities.

14 . The semiconductor device of claim 9 , wherein a cross-section of the first source/drain layer, according to the first direction and the vertical direction, has a concave upper surface.

15 . A semiconductor device, comprising:
a substrate; a first source/drain pattern and a second source/drain pattern spaced apart in a first direction on the substrate; a height from an upper surface of a central portion of the first source/drain pattern to an upper surface of the substrate in a vertical direction is higher than, or a same height as, a height from an upper surface of an edge of the first source/drain pattern to the upper surface of the substrate in the vertical direction

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yi Yunyeong
• Kang Myung Gil
• Kwon Wookhyun
• Kim Younggwon
• Kim Jong Pil
• Jeong Soojin
• Hong Byoung Hak

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title