Display driving apparatus, and display apparatus having the same

Patent metadata

Field	Value
Publication number	US-2026046472-A1
Application number	US-202519060406-A
Country	US
Kind code	A1
Filing date	Feb 21, 2025
Priority date	Aug 12, 2024
Publication date	Feb 12, 2026
Grant date	—

Abstract

A display apparatus includes: a video processing unit processing a video signal; a graphics processing unit processing a graphics signal; a mixing unit mixing video corresponding to the processed video signal and graphics corresponding to the processed graphics signal; a display unit outputting the mixed video and graphics; and a main processing unit configured to control the video processing unit, the graphics processing unit, the mixing unit and the display unit.

First claim

What is claimed is:

1 . A display apparatus, comprising:
a video processor configured to process a video signal; a graphics processor configured to process a graphics signal; a mixing processor configured to mix the processed video signal and the processed graphics signal to provide a mixed video and graphics signal; a display device configured to output the mixed video and graphics signal; and a main processor configured to control the video processor, the graphics processor, the mixing processor, and the display device, wherein the video signal includes a plurality of video frames, and the graphics signal includes a plurality of graphics frames, and wherein the main processor is configured to
calculate, for each video frame of the plurality of video frames, a respective video delay time using both a video rendering request time at which rendering is requested for the video frame and a video output time at which the video frame is output to the display device,
calculate, for each graphics frame of the plurality of graphics frames, a respective graphics delay time using both a graphics rendering request time at which rendering is requested for the graphics frame and a graphics output time at which the graphics frame is output to the display device, and
synchronize the plurality of video frames and the plurality of graphics frames by compensating at least one video delay time, at least one graphics delay time, or at least one video delay time and at least one graphics delay time.

2 . The display apparatus of claim 1 ,
wherein, for each video frame, the respective video delay time is a time from the video rendering request time for the video frame to the video output time for the video frame, and wherein, for each graphics frame, the respective graphics delay time is a time from the graphics rendering request time for the graphics frame to the graphics output time for the graphics frame.

3 . The display apparatus of claim 1 , wherein the main processor is configured to store the video rendering request time and the graphics rendering request time in context data.

4 . The display apparatus of claim 1 , wherein the main processor is configured to:
insert an output order of the plurality of video frames into each video frame of the plurality of video frames as a video binarization pattern, and calculate the video rendering request time by analyzing the video binarization pattern; and insert an output order of the plurality of graphics frames into each graphics frame of the plurality of graphics frames as a graphics binarization pattern, and calculate the graphics rendering request time by analyzing the graphics binarization pattern.

5 . The display apparatus of claim 1 ,
wherein the video processor includes a plurality of video processing components, wherein the graphics processor includes a plurality of graphics processing components, and wherein a number of the plurality of video processing components is greater than a number of the plurality of graphics processing components.

6 . The display apparatus of claim 5 , wherein, for at least one of the plurality of video frames, the video delay time is longer than the graphics delay time.

7 . The display apparatus of claim 5 , wherein the main processor is configured to:
calculate a first video-graphics delay time, wherein the video-graphics delay time is a difference between a first video delay time and a first graphics delay time; and compensate the first video delay time, the first graphics delay time, or both the first video delay time and the first graphics delay time based on the video-graphics delay time.

8 . The display apparatus of claim 7 , wherein the main processor is configured to compensate the first video delay time based on geometry information from the plurality of video frames.

9 . The display apparatus of claim 8 , wherein the geometry information includes sizes and positions of each video frame of the plurality of video frames.

10 . The display apparatus of claim 9 , wherein the main processing unit is configured to:
calculate a change frequency of the geometry information of the plurality of video frames; and shorten the first video delay time when the change frequency of the geometry information is greater than or equal to a reference frequency.

11 . The display apparatus of claim 10 , wherein the main processor is configured to shorten the first video delay time by the video-graphics delay time by implementing less than all of the plurality of video processing components.

12 . The display apparatus of claim 9 , wherein the main processor is configured to shorten the first video delay time based on sizes of the plurality of video frames being less than or equal to a reference size.

13 . The display apparatus of claim 12 , wherein the main processor is configured to shorten the first video delay time by the video-graphics delay time by implementing less than all of the plurality of video processing components.

14 . The display apparatus of claim 7 , further comprising:
a memory circuit that includes a video buffer configured to store a video signal processed by the video processor and a graphics buffer configured to store a graphics signal processed by the graphics processor.

15 . The display apparatus of claim 14 , wherein the main processor is configured to allocate an additional graphics buffer corresponding to the video-graphics delay time, and include the additional graphics buffer in the graphics buffer to extend the graphics delay time.

16 . A display apparatus, comprising:
a video processor configured to process a video signal including a plurality of video frames, the video processor including a plurality of video processing components; a graphics processor configured to process a graphics signal that includes a plurality of graphics frames, the graphics processor including a plurality of graphics processing components; a mixing processor configured to mix the processed video signal and the processed graphics signal to provide a mixed video and graphics signal; a display device configured to output the mixed video and graphics signal; and a main processor configured to control the video processor, the graphics processor, the mixing processor, and the display device, wherein a number of the plurality of video processing components is greater than a number of the plurality of graphics processing components, and wherein the main processor is configured to
shorten, for each of the plurality of video frames, a respective video delay time using a time at which each of the plurality of video frames is output to the display device, or
extend, for each graphics frame of the plurality of graphics frames, a respective graphics delay time using a time at which each of the plurality of graphics frames is output to the display device.

17 . The display apparatus of claim 16 , wherein, for at least one of the plurality of video frames, the video delay time is longer than the graphics delay time.

18 . The display apparatus of claim 17 , wherein the main processor is configured to: shorten the video delay time by the difference in delay time by implementing less than all of the plurality of video processing components, when a change frequency of geometry information of the plurality of video frames is greater than or equal to a reference frequency or sizes of the plurality of frames are lower than or equal to a reference size.

19 . The display apparatus of claim 17 , further comprising:
a memory circui

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Taehong
• Choi Joohee
• Kim Dayoung
• Shin Soyoung

Classifications

• G06F3/14

  Digital output to display device {; Cooperation and interconnection of the display device with other functional units} · CPC title

• H04N21/8146 Primary

  involving graphical data, e.g. 3D object, 2D graphics · CPC title

• H04N21/44012

  involving rendering scenes according to scene graphs, e.g. MPEG-4 scene graphs · CPC title

• H04N21/43072

  of multiple content streams on the same device · CPC title

• H04N5/265

  Mixing · CPC title