Compute-in-memory cell and array with capacitive accumulation and nonvolatile memory transistor

Patent metadata

Field	Value
Publication number	US-2026045288-A1
Application number	US-202519216231-A
Country	US
Kind code	A1
Filing date	May 22, 2025
Priority date	Aug 6, 2024
Publication date	Feb 12, 2026
Grant date	—

Abstract

A CiM architecture is disclosed, including memory cells each having a nonvolatile memory transistor and a capacitor connected in series between a bit line and a sense node. The transistor is configured to store a programmable state corresponding to a weight value and to selectively conduct based on a control voltage applied to a gate terminal. During a charging phase, the capacitor accumulates charge based on the conduction state of the transistor and an input voltage applied to the bit line. During a compute phase, the sense node exchanges charge with one or more other sense nodes in the array, such that a resulting voltage reflects an analog output of a MAC operation. The disclosed architecture can support binary and/or multi-bit computation and, in some cases, can utilize FeFETs or other nonvolatile devices to perform in-memory operations with improved variation resilience and energy efficiency.

First claim

What is claimed is:

1 . A compute-in-memory cell for use in an array of compute-in-memory cells, the compute-in-memory cell comprising:
a nonvolatile memory transistor having a gate terminal, a first terminal, and a second terminal, the nonvolatile memory transistor configured to retain a programmable state corresponding to a threshold voltage, and to selectively conduct in response to a control voltage applied to the gate terminal; a capacitor electrically coupled in series with the nonvolatile memory transistor between a bit line and a sense node, the capacitor configured to accumulate electrical charge from the bit line during a charging phase when the nonvolatile memory transistor conducts; wherein the bit line is configured to supply an input voltage during the charging phase, and the sense node is configured to store charge representative of a weight value associated with the compute-in-memory cell; and wherein the sense node is further configured to transfer charge to or receive charge from one or more other sense nodes in the array during a compute phase, such that a voltage at the sense node reflects an analog output of a multiply-accumulate operation.

2 . The compute-in-memory cell of claim 1 , wherein the programmable state of the nonvolatile memory transistor corresponds to a binary weight value, and wherein the capacitor is configured to store either a nonzero charge or substantially no charge based on whether the nonvolatile memory transistor conducts during the charging phase.

3 . The compute-in-memory cell of claim 1 , wherein the programmable state of the nonvolatile memory transistor corresponds to a multi-bit weight value, and wherein the capacitor is configured to store one of a plurality of discrete charge levels corresponding to the multi-bit weight value.

4 . The compute-in-memory cell of claim 1 , wherein the nonvolatile memory transistor functions as a switch to control whether the capacitor accumulates charge during the charging phase based on the programmable state of the transistor.

5 . The compute-in-memory cell of claim 1 , wherein the nonvolatile memory transistor comprises a ferroelectric field-effect transistor having a gate stack including at least one ferroelectric dielectric layer configured to retain a polarization state corresponding to a threshold voltage.

6 . The compute-in-memory cell of claim 1 , wherein the charging phase comprises applying a sequence of input voltages to the bit line and a corresponding sequence of control voltages to the gate terminal of the nonvolatile memory transistor to incrementally charge the capacitor in accordance with a stored multi-bit weight value.

7 . The compute-in-memory cell of claim 1 , wherein the compute phase includes floating the bit line and connecting the sense node to one or more additional sense nodes through a shared line to perform analog charge redistribution across multiple cells.

8 . The compute-in-memory cell of claim 1 , wherein the capacitor is configured to be discharged to a baseline voltage prior to the charging phase.

9 . The compute-in-memory cell of claim 1 , wherein the sense node is configured to interface with peripheral circuitry to convert the voltage at the sense node into a digital output corresponding to a computed result.

10 . The compute-in-memory cell of claim 1 , wherein the programmable state of the nonvolatile memory transistor is retained without requiring periodic refresh, and wherein charge-based computation is performed without destructively reading the programmable state of the nonvolatile memory transistor.

11 . A compute-in-memory array comprising a plurality of compute-in-memory cells arranged in rows and columns, each compute-in-memory cell comprising:
a nonvolatile memory transistor having a gate terminal, a first terminal, and a second terminal, the nonvolatile memory transistor configured to retain a programmable state corresponding to a threshold voltage and to selectively conduct in response to a control voltage applied to the gate terminal; a capacitor electrically coupled in series with the nonvolatile memory transistor between a bit line and a sense node, the capacitor configured to accumulate electrical charge during a charging phase when the nonvolatile memory transistor conducts; wherein the gate terminals of the nonvolatile memory transistors in a row are coupled to a common word line, and the bit lines and sense nodes are shared among compute-in-memory cells in respective columns; wherein the compute-in-memory array is configured to perform a multiply-accumulate operation by applying control voltages to selected word lines and input voltages to selected bit lines to conditionally charge capacitors in the compute-in-memory cells based on stored weight values, and wherein the sense nodes are configured to redistribute charge among capacitors during a compute phase such that a voltage at a sense node represents an analog output of the multiply-accumulate operation.

12 . The compute-in-memory array of claim 11 , wherein each compute-in-memory cell is configured to perform computation by accumulating electrical charge on its capacitor during a charging phase and by participating in charge redistribution across a plurality of sense nodes during a compute phase, such that a voltage level developed at a sense node corresponds to a cumulative charge value that represents the analog output of the multiply-accumulate operation.

13 . The compute-in-memory array of claim 11 , wherein each compute-in-memory cell is configured to store a multi-bit weight value, and wherein the capacitor in each compute-in-memory cell is configured to accumulate one of a plurality of discrete charge levels in response to a sequence of control voltages applied to the corresponding word line and a sequence of input voltages applied to the corresponding bit line.

14 . The compute-in-memory array of claim 11 , further comprising a peripheral circuit configured to sample the voltage at each sense node after charge redistribution, and to convert the sampled voltage into a digital value representing the analog output of the multiply-accumulate operation.

15 . A method of performing a multiply-accumulate operation in a compute-in-memory array comprising a plurality of compute-in-memory cells, each compute-in-memory cell comprising a nonvolatile memory transistor and a capacitor, the method comprising:
storing a weight value by programming the nonvolatile memory transistor to a selected programmable state; applying an input voltage to a bit line and a control voltage to a word line to cause the nonvolatile memory transistor to selectively conduct based on the programmable state; accumulating charge on the capacitor during a charging phase when the nonvolatile memory transistor conducts; and transferring charge to or receiving charge from one or more additional capacitors associated with other compute-in-memory cells via interconnected sense nodes during a compute phase, such that a voltage on a sense node represents a result of the multiply-accumulate operation.

16 . The method of claim 15 , wherein the nonvolatile memory transistor comprises a ferroelectric field-effect transistor having a gate stack including a ferroelectric dielectric layer configured to retain a polarization state corresponding to a threshold voltage of the transistor.

17 . The method of claim 15 , further comprising discharging the capacitor to a baseline voltage prior to the charging phase to initialize the compute-in-memory cell for the multiply-accumulate operation.

Assignees

• Univ Notre Dame Du Lac
• Penn State Res Found

Inventors

• Ni Kai
• Narayanan Vijaykrishnan
• Xu Yixin

Classifications

• G11C11/5657

  using ferroelectric storage elements · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C11/223

  using MOS with ferroelectric gate insulating film · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title