Gate driving circuit, display device including the gate driving circuit and electronic device including the display device

Patent metadata

Field	Value
Publication number	US-2026045205-A1
Application number	US-202519212441-A
Country	US
Kind code	A1
Filing date	May 19, 2025
Priority date	Aug 8, 2024
Publication date	Feb 12, 2026
Grant date	—

Abstract

A gate driver may include stages for outputting first and second gate signals, the stages including a control circuit configured to control a voltage of a pull-up control node and a voltage of a first pull-down control node in response to an input signal and a first clock signal, and configured to output a carry signal at a carry output node in response to the voltage of the pull-up control node or the voltage of the first pull-down control node, a first output circuit configured to output the first gate signal at a first output node in response to the voltage of the pull-up control node or a voltage of the carry output node, and a second output circuit configured to output the second gate signal at a second output node in response to the voltage of the pull-up control node or the voltage of the carry output node.

First claim

What is claimed is:

1 . A gate driver comprising:
stages each outputting two or more gate signals, wherein each of the stages comprises:
a control circuit configured to control a voltage of a pull-up control node and a voltage of a first pull-down control node in response to an input signal and a first clock signal, and configured to output a carry signal at a carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node;
a first output circuit configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and a voltage of the carry output node; and
a second output circuit configured to output a second gate signal at a second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

2 . The gate driver of claim 1 , wherein the control circuit comprises:
a first transistor comprising a control electrode configured to receive the first clock signal, a first electrode configured to receive the input signal, and a second electrode connected to a buffer node; a second transistor comprising a control electrode connected to the buffer node, a first electrode configured to receive a first power supply voltage, and a second electrode connected to the pull-up control node; a third transistor comprising a control electrode, a first electrode connected to the pull-up control node, and a second electrode configured to receive a second power supply voltage; a fourth transistor comprising a control electrode configured to receive the second power supply voltage, a first electrode connected to the buffer node, and a second electrode connected to the first pull-down control node; a fifth transistor comprising a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the carry output node; a sixth transistor comprising a control electrode connected to the first pull-down control node, a first electrode connected to the carry output node, and a second electrode configured to receive the second power supply voltage; a first capacitor comprising a first electrode configured to receive the first power supply voltage, and a second electrode connected to the pull-up control node; and a second capacitor comprising a first electrode connected to the carry output node, and a second electrode connected to the first pull-down control node.

3 . The gate driver of claim 2 , wherein the control electrode of the third transistor is connected to the first pull-down control node.

4 . The gate driver of claim 2 , wherein the control electrode of the third transistor is connected to the buffer node.

5 . The gate driver of claim 2 , wherein the third transistor comprises an N-channel metal oxide semiconductor (NMOS) transistor.

6 . The gate driver of claim 2 , wherein the first output circuit comprises:
a seventh transistor comprising a control electrode configured to receive the second power supply voltage, a first electrode connected to the carry output node, and a second electrode connected to a second pull-down control node; an eighth transistor comprising a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the first output node; a ninth transistor comprising a control electrode connected to the second pull-down control node, a first electrode connected to the first output node, and a second electrode configured to receive a second clock signal; and a third capacitor comprising a first electrode connected to the first output node, and a second electrode connected to the second pull-down control node.

7 . The gate driver of claim 6 , wherein a ratio of a channel width to a channel length of at least one of the seventh transistor, the eighth transistor, or the ninth transistor is different from a ratio of a channel width to a channel length of at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, or the sixth transistor.

8 . The gate driver of claim 7 , wherein the ratio of the channel width to the channel length of the at least one of the seventh transistor, the eighth transistor, or the ninth transistor is greater than the ratio of the channel width to the channel length of the at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, or the sixth transistor.

9 . The gate driver of claim 2 , wherein the second output circuit comprises:
a tenth transistor comprising a control electrode configured to receive the second power supply voltage, a first electrode connected to the carry output node, and a second electrode connected to a third pull-down control node; an eleventh transistor comprising a control electrode connected to the pull-up control node, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the second output node; a twelfth transistor comprising a control electrode connected to the third pull-down control node, a first electrode connected to the second output node, and a second electrode configured to receive a third clock signal; and a fourth capacitor comprising a first electrode connected to the second output node, and a second electrode connected to the third pull-down control node.

10 . The gate driver of claim 9 , wherein a ratio of a channel width to a channel length of at least one of the tenth transistor, the eleventh transistor, or the twelfth transistor is different from a ratio of a channel width to a channel length of at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, or the sixth transistor.

11 . The gate driver of claim 10 , wherein the ratio of the channel width to the channel length of the at least one of the tenth transistor, the eleventh transistor, or the twelfth transistor is greater than the ratio of the channel width to the channel length of the at least one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, or the sixth transistor.

12 . A display device comprising:
a display panel comprising pixels; a data driver configured to provide data voltages to the display panel; a gate driver configured to provide gate signals to the display panel; and a driving controller configured to control the data driver and the gate driver, wherein the gate driver includes stages each outputting two or more the gate signals.

13 . The display device of claim 12 , wherein each of the stages comprises:
a control circuit configured to control a voltage of a pull-up control node and a voltage of a first pull-down control node in response to an input signal and a first clock signal, and configured to output a carry signal at a carry output node in response to the voltage of the pull-up control node and the voltage of the first pull-down control node; a first output circuit configured to output a first gate signal at a first output node in response to the voltage of the pull-up control node and a voltage of the carry output node; and a second output circuit configured to output a second gate signal at a second output node in response to the voltage of the pull-up control node and the voltage of the carry output node.

14 . The display device of claim 13 , wherein the control circuit

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Sanghun
• Keum Nackhyeon
• Kim Yongchan

Classifications

• G09G3/2077

  by a combination of two or more gradation control methods · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title