Electrical interconnects for packages containing photonic integrated circuits

US2026041015A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2026041015-A1
Application numberUS-202519356023-A
CountryUS
Kind codeA1
Filing dateOct 10, 2025
Priority dateDec 29, 2023
Publication dateFeb 5, 2026
Grant date

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  5. First independent claim

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Abstract

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A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that the electrical component is electrically connected to the active photonic component. The landing pad has a larger surface area than a cross sectional area of the copper pillar, and wherein, when viewed from the EIC towards the PIC, the active photonic component on the PIC is offset from the landing pad of the EIC, wherein the offset is sufficient to keep a parasitic capacitance between the landing pad and the active photonic component within a pre-determined threshold level of tolerance.

First claim

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What is claimed is: 1 . A device comprising: a power controller; a substrate; a package supported by the substrate, the package comprising: photonic integrated circuit (PIC) comprising at least one active photonic component configured to operate on a photonic signal; an electronic integrated circuit (EIC) mounted on the PIC on a surface opposite the substrate, the EIC comprising at least one analog-mixed signal (AMS) block electrically connected a corresponding one of the at least one active photonic component, the at least one AMS block being separated from the corresponding active photonic component by less than 100 μm; and a first electrical interconnect electrically connecting the power controller with the EIC through the PIC, wherein the device is configured to deliver electrical power from the power controller to the at least one AMS block on the EIC through the PIC and the substrate during operation of the device. 2 . The device of claim 1 , wherein the first electrical interconnect comprises: at least one flip-chip bump between the surface of the PIC and a surface the EIC that is facing the surface of the PIC. 3 . The device of claim 2 , wherein the first electrical interconnect further comprises conductive traces in the substrate that are electrically connected to the power controller. 4 . The device of claim 3 , wherein the first electrical interconnect further comprises through silicon vias (TSVs) in the PIC that are electrically connected to the conductive traces of the substrate. 5 . The device of claim 1 , wherein each of the at least one active photonic component comprises: a modulator, or a photo diode, connected to a first landing pad at the surface of the PIC. 6 . The device of claim 5 , wherein the corresponding AMS block comprises: a driver or a transimpedance amplifier (TIA), and the corresponding AMS block is electrically connected to a second landing pad at the surface of the EIC facing the surface of the PIC. 7 . The device of claim 6 , wherein said second landing pad is electrically connected to a corresponding first landing pad via a flip-chip bump. 8 . The device of claim 5 , wherein, when viewed from the EIC towards the PIC, a center of each modulator is offset from a nearest edge of the corresponding first landing pad by about a distance less than 10 μm. 9 . The device of claim 5 , wherein each modulator is one of: an electro-absorption modulator (EAM), a ring modulator, an interference-based modulator. 10 . The device of claim 5 , wherein each modulator comprises a diode junction, a cathode, and an anode. 11 . The device of claim 10 , wherein the corresponding first landing pad of each modulator is electrically connected to the cathode of the modulator. 12 . The device of claim 10 , wherein the anode of each modulator is electrically connected to a bias voltage. 13 . The device of claim 12 , wherein the PIC comprises a temperature sensor electrically connected to the EIC. 14 . The device of claim 13 , further comprising a second electrical interconnect that electrically connects the anode of at least one modulator with the power controller, wherein the EIC is configured to adjust the bias voltage on the anode of the at least one modulator based on, at least in part, one or more measurements from the temperature sensor. 15 . The device of claim 5 , wherein the at least one AMS block comprises a driver. 16 . The device of claim 15 , wherein the driver and the modulator are spaced apart by about 2 mm or less. 17 . The device of claim 1 , wherein the at least one active photonic component comprises a photodiode and a modulator, wherein the PIC comprises a bidirectional photonic link that comprises the photodiode and the modulator, wherein the bidirectional photonic link further comprises a first waveguide connecting the modulator to a unit coupled to one or more fibers, and a second waveguide connecting the photodiode to the unit coupled to the one or more fibers, and wherein the first waveguide and the second waveguide are configured to support the photonic signal. 18 . The device of claim 17 , wherein the at least one AMS block comprises a driver electrically connected to a corresponding modulator in the PIC, and a transimpedance amplifier electrically connected to a corresponding photodiode in the EIC. 19 . The device of claim 18 , further comprising a heat sink mounted on a surface of the EIC that is opposite the PIC. 20 . The device of claim 18 , further comprising a processor mounted on the PIC, wherein the processor is configured to be electrically powered from underneath through the PIC and the substrate. 21 . The device of claim 20 , further comprising a heat sink mounted on a surface of the processor that is opposite the PIC.

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What does patent US2026041015A1 cover?
A system-in-package includes: a photonic integrated circuit (PIC) including an active photonic component; and an electronic integrated circuit (EIC) stacked on the PIC, the EIC including: an electrical component electrically connected to a landing pad, and a copper pillar embedded in the landing pad and protruding from the landing pad that connects with the active photonic component such that t…
Who is the assignee on this patent?
Celestial Ai Inc
What technology area does this patent fall under?
Primary CPC classification H01L25/167. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Feb 05 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).