Semiconductor devices and data storage systems including the same

Patent metadata

Field	Value
Publication number	US-2026040581-A1
Application number	US-202519088052-A
Country	US
Kind code	A1
Filing date	Mar 24, 2025
Priority date	Aug 5, 2024
Publication date	Feb 5, 2026
Grant date	—

Abstract

A semiconductor device may include a first semiconductor structure including a substrate, circuit devices on the substrate, a first interconnection structure electrically coupled to the circuit devices, and a first bonding metal layer on the circuit devices and the first interconnection structure, a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure, and the second semiconductor structure including a memory cell substrate including a conductive pattern and an insulating pattern in contact with a side surface of the conductive pattern, gate electrodes stacked and spaced apart from each other below the memory cell substrate, channel structures penetrating the gate electrodes and spaced apart from each other in a first direction, a second interconnection structure below the gate electrodes and the channel structures, a second bonding metal layer below the second interconnection structure, and the second bonding metal layer connected to the first bonding metal layer.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first semiconductor structure including
a substrate,
circuit devices on the substrate,
a first interconnection structure electrically coupled to the circuit devices, and
a first bonding metal layer on the circuit devices and the first interconnection structure; and
a second semiconductor structure connected to the first semiconductor structure on the first semiconductor structure; and the second semiconductor structure including
a memory cell substrate including a conductive pattern and an insulating pattern in contact with a side surface of the conductive pattern,
gate electrodes stacked and spaced apart from each other below the memory cell substrate in a perpendicular direction, the perpendicular direction being perpendicular to a lower surface of the memory cell substrate,
channel structures
penetrating the gate electrodes,
extending into the memory cell substrate in the perpendicular direction, and

the channel structures spaced apart from each other in a first direction, the first direction intersecting the perpendicular direction,
a second interconnection structure below the gate electrodes and the channel structures, and
a second bonding metal layer below the second interconnection structure, and
the second bonding metal layer connected to the first bonding metal layer,
wherein each of the channel structures includes
a first channel hole penetrating the gate electrodes in the perpendicular direction,
a second channel hole penetrating the gate electrodes in the perpendicular direction,
the second channel hole spaced apart from the first channel hole,
a first channel pattern including
a first channel portion in the first channel hole,
a second channel portion in the second channel hole, and
a first channel connection portion extending from the first channel portion and the second channel portion on the gate electrodes,

the first channel pattern connecting the first channel portion to the second channel portion, and
the conductive pattern overlapping the first channel hole in the perpendicular direction and not overlapping the second channel hole.

2 . The semiconductor device of claim 1 , wherein
each of the channel structures further includes
a first data storage pattern in the first channel hole,
a second data storage pattern in the second channel hole, and
a channel filling insulating layer surrounded by the first channel pattern, and
the first channel connection portion extends above the first and second data storage patterns.

3 . The semiconductor device of claim 2 , wherein
the channel filling insulating layer includes
a first insulating portion surrounded by the first channel portion,
a second insulating portion surrounded by the second channel portion, and
a third insulating portion extending from the first insulating portion and the second insulating portion,
the third insulating portion connecting the first insulating portion to the second insulating portion, and the third insulating portion surrounded by the first channel connection portion.

4 . The semiconductor device of claim 2 , wherein
the first data storage pattern includes
a first tunneling layer surrounding the first channel portion,
a first data storage layer surrounding the first tunneling layer,
a first blocking layer surrounding the first data storage layer, and
the first blocking layer in contact with the gate electrodes, and
the second data storage pattern includes
a second tunnelling layer surrounding the second channel portion,
a second data storage layer surrounding the second tunnelling layer, and
a second blocking layer surrounding the second data storage layer, and
the second blocking layer in contact with the gate electrodes.

5 . The semiconductor device of claim 2 , wherein
the first channel hole and the second channel hole are spaced apart from each other in a third direction, the third direction between the first direction and a second direction, and the second direction intersecting the first direction and the perpendicular direction.

6 . The semiconductor device of claim 1 , further comprising:
a first interconnection extending in a second direction, the second direction intersecting the first direction and the perpendicular direction, the first interconnection connected to the first channel hole, and a second interconnection spaced apart from the first interconnection in the first direction, and the second interconnection connected to the second channel hole.

7 . The semiconductor device of claim 1 , wherein
the conductive pattern extends in the first direction, a portion of the first channel connection portion of the first channel pattern is in contact with the conductive pattern, and another portion of the first channel connection portion of the first channel pattern is not in contact with the conductive pattern.

8 . The semiconductor device of claim 1 , wherein
each of the channel structures includes:
a third channel hole penetrating the gate electrodes in the perpendicular direction;
a fourth channel hole penetrating the gate electrodes in the perpendicular direction and spaced apart from the third channel hole; and
a second channel pattern including
a third channel portion in the third channel hole,
a fourth channel portion in the fourth channel hole,
a second channel connection portion extending from the third channel portion and the fourth channel portion, and
the second channel connection portion connecting the third channel portion to the fourth channel portion on the gate electrodes;

the third channel hole is spaced apart from the first channel hole in a second direction, the second direction intersecting the first direction and the perpendicular direction; and the fourth channel hole is spaced apart from the second channel hole in the second direction.

9 . The semiconductor device of claim 8 , wherein the conductive pattern overlaps the third channel hole in the perpendicular direction and does not overlap the fourth channel hole.

10 . The semiconductor device of claim 8 , wherein the first channel pattern and the second channel pattern are spaced apart from each other in the second direction.

11 . The semiconductor device of claim 8 , wherein the first channel connection portion of the first channel pattern and the second channel connection portion of the second channel pattern are connected to and integrated with each other.

12 . The semiconductor device of claim 8 , wherein the first to fourth channel holes intersect each other in order in the second direction and are in a zigzag pattern.

13 . The semiconductor device of claim 1 , wherein each of the channel structures further includes a conductive liner covering the first channel connection portion of the first channel pattern.

14 . A semiconductor device, comprising:
a first semiconductor structure including
a substrate,
circuit devices on the substrate, and
first interconnection structure on the circuit devices, and
a second semiconductor structure on the first semiconductor structure; the second semiconductor structure including
a memory cell substrate including conductive patterns spaced apart from each other,
gate electrodes including
an upper select gate electrode,
memory gate electrodes,
a lower select gate electrode stacked and spaced apart from each other in a perpendicular direction, the perpendicular direction being perpendicular to a lower surface of the memory cell substrate below the memory cell substrate, and
the upper select gate elec

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sangyong
• Moon Kibong
• Lee Sungbok
• Lee Jaeduk

Classifications

• H01L2924/14511

  Electricity · mapped topic

• H01L2924/1431

  Electricity · mapped topic

• H01L2224/80896

  Electricity · mapped topic

• H01L2224/80895

  Electricity · mapped topic

• H01L2224/08145

  Electricity · mapped topic