Semiconductor memory device and method for manufacturing semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2026040547-A1
Application number	US-202519058222-A
Country	US
Kind code	A1
Filing date	Feb 20, 2025
Priority date	Jul 30, 2024
Publication date	Feb 5, 2026
Grant date	—

Abstract

According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, a pillar penetrating the stacked body, and a contact. The stacked body has a staircase portion in which a terrace portion of the plurality of conductive layers is processed in a staircase shape. The contact penetrates the terrace portion of one conductive layer and lower conductive layers below the one conductive layer in the staircase portion. The one conductive layer is electrically connected to the contact in the terrace portion. Both surfaces of each of the plurality of conductive layers in the stacking direction including the terrace portion are covered with a first metal-containing layer. In each of the lower conductive layers, an end surface facing the contact is covered with the first metal-containing layer.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked, wherein the stacked body has a staircase portion in which a terrace portion of the plurality of conductive layers is processed in a staircase shape; a pillar that penetrates the stacked body at a position away from the staircase portion in a first direction intersecting a stacking direction of the stacked body; and a contact that penetrates the terrace portion of one conductive layer among the plurality of conductive layers and lower conductive layers below the one conductive layer in the staircase portion, the one conductive layer being electrically connected to the contact in the terrace portion, wherein, in the terrace portion, each of the plurality of conductive layers has a layer thickness smaller than a layer thickness of each of the plurality of conductive layers in a region in which the pillar is disposed, both surfaces of each of the plurality of conductive layers in the stacking direction including the terrace portion are covered with a first metal-containing layer, in each of the lower conductive layers which the contact penetrates, an end surface facing the contact is covered with the first metal-containing layer.

2 . The semiconductor memory device according to claim 1 ,
wherein the first metal-containing layer is a metal oxide layer and is not disposed on an end surface of the one conductive layer facing the contact.

3 . The semiconductor memory device according to claim 1 ,
wherein the contact includes: a conductive first flange portion that protrudes from a side wall of the contact toward the one conductive layer; and a plurality of insulating second flange portions that protrude from the side wall of the contact toward the lower conductive layers and are in contact with the first metal-containing layers covering the end surfaces of the lower conductive layers.

4 . The semiconductor memory device according to claim 3 , wherein a layer thickness of the first flange portion is substantially equal to a layer thickness of the one conductive layer.

5 . The semiconductor memory device according to claim 3 , wherein a layer thickness of the plurality of insulating second flange portions is substantially equal to a layer thickness of the lower conductive layers.

6 . The semiconductor memory device according to claim 3 ,
wherein a protrusion distance of the first flange portion from the side wall of the contact is smaller than a protrusion distance of each of the plurality of second flange portions from the side wall of the contact.

7 . The semiconductor memory device according to claim 3 ,
wherein the first flange portion has the same material as a main body portion of the contact and is configured integrally with the main body portion of the contact.

8 . The semiconductor memory device according to claim 3 ,
wherein the first flange portion does not have a portion overlapping, in a height direction, a conductive layer adjacent to the one conductive layer in the stacking direction.

9 . The semiconductor memory device according to claim 1 ,
wherein the lower conductive layers are not electrically connected to the contact in the terrace portion.

10 . The semiconductor memory device according to claim 1 ,
an end portion facing the contact in the first metal-containing layer that covers both surfaces of the one conductive layer, is located closer to the contact than an end portion facing the contact in the first metal-containing layer that covers both surfaces of each of the lower conductive layers.

11 . A method for manufacturing a semiconductor memory device, the method comprising:
forming a stacked body in which a plurality of first sacrificial layers and a plurality of first insulating layers are alternately stacked; processing a terrace portion of each of the plurality of first sacrificial layers in a staircase shape to form a staircase portion of the stacked body; thinning the terrace portion of each of the plurality of first sacrificial layers; forming a pillar that penetrates the stacked body at a position away from the staircase portion in a first direction intersecting a stacking direction of the stacked body; forming a contact hole that penetrates the terrace portion of one first sacrificial layer among the plurality of first sacrificial layers and lower first sacrificial layers below the one first sacrificial layer in the staircase portion; retreating the one first sacrificial layer and the lower first sacrificial layers, which are exposed to a side wall of the contact hole, from the side wall to form a first flange portion that protrudes toward the one first sacrificial layer on the side wall of the contact hole at a height position of the one first sacrificial layer and to form a plurality of second flange portions that protrude toward the lower first sacrificial layers on the side wall of the contact hole at height positions of the lower first sacrificial layers; filling each of the plurality of second flange portions with a second insulating layer; replacing each of the plurality of first sacrificial layers with a conductive material to form one first conductive layer from the one first sacrificial layer and to form lower first conductive layers from the lower first sacrificial layers; and filling the contact hole and the first flange portion with a second conductive layer to form a contact connected to the one first conductive layer in the terrace portion of the one first conductive layer.

12 . The method for manufacturing a semiconductor memory device according to claim 11 ,
wherein the retreating of the one first sacrificial layer and the lower first sacrificial layers includes: more retreating the lower first sacrificial layers from the side wall of the contact hole than retreating the one first sacrificial layer, using a difference in layer thickness between the one first sacrificial layer and the lower first sacrificial layers.

13 . The method for manufacturing a semiconductor memory device according to claim 11 ,
wherein the retreating of the one first sacrificial layer and the lower first sacrificial layers includes: more retreating the lower first sacrificial layers from the side wall of the contact hole than retreating the one first sacrificial layer, so that a retreat distance of the one first sacrificial layer from the side wall is smaller than a retreat distance of the lower first sacrificial layers from the side wall.

14 . The method for manufacturing a semiconductor memory device according to claim 11 ,
wherein the filling of the plurality of second flange portions with the second insulating layer includes: filling the first flange portion with a second sacrificial layer.

15 . The method for manufacturing a semiconductor memory device according to claim 14 ,
wherein the filling of the plurality of second flange portions with the second insulating layer further includes: filling each of the plurality of second flange portions with the second insulating layer after filling the first flange portion with the second sacrificial layer.

16 . The method for manufacturing a semiconductor memory device according to claim 14 ,
wherein the filling of the first flange portion with the second sacrificial layer includes: forming the second sacrificial layer that covers the side wall of the contact hole with a layer thickness where the first flange portion is filled with the second sacrificial layer and the plurality

Assignees

• Kioxia Corp

Inventors

• Noda Kosei

Classifications

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title