Tuning of superconducting tunnel junction devices using microfabricated heaters

Patent metadata

Field	Value
Publication number	US-2026033249-A1
Application number	US-202418642380-A
Country	US
Kind code	A1
Filing date	Apr 22, 2024
Priority date	Apr 22, 2024
Publication date	Jan 29, 2026
Grant date	—

Abstract

Techniques are provided for tuning junction resistances of superconducting tunnel junction devices (e.g., Josephson junctions) by localized thermal annealing of the superconducting tunnel junction devices. An exemplary embodiment includes a device which comprises a substrate, a quantum device comprising a superconducting tunnel junction device disposed on the substrate, and at least one heater element disposed on the substrate. The at least one heater element is configured to generate heat through resistive heating in response to a current applied to the at least one heater element, to heat a region of the substrate on which the superconducting tunnel junction device is disposed to thermally anneal the superconducting tunnel junction device.

First claim

What is claimed is:

1 . A device, comprising:
a substrate; a quantum device comprising a superconducting tunnel junction device disposed on the substrate; and at least one heater element disposed on the substrate and configured to generate heat through resistive heating in response to a current applied to the at least one heater element, to heat a region of the substrate on which the superconducting tunnel junction device is disposed to thermally anneal the superconducting tunnel junction device.

2 . The device of claim 1 , wherein:
the at least one heater element comprises at least one contact pad and a resistive element connected to the at least one contact pad; and the at least one heater element is disposed within a patterned void of a metallization feature on a surface of the substrate.

3 . The device of claim 2 , wherein the resistive element is serially connected to and between the at least one contact pad and the metallization feature.

4 . The device of claim 2 , wherein:
the at least one contact pad comprises a first contact pad and a second contact pad; and the resistive element is serially connected to and between the first contact pad and the second contact pad.

5 . The device of claim 2 , wherein the metallization feature comprises superconducting pad of the quantum device.

6 . The device of claim 2 , wherein the metallization feature comprises a ground plane disposed on a surface of the substrate.

7 . The device of claim 2 , wherein the resistive element comprises a patterned metal trace.

8 . The device of claim 2 , wherein the resistive element comprises a doped region of the substrate.

9 . The device of claim 1 , wherein the quantum device and the at least one heater element are disposed on a same side of the substrate.

10 . The device of claim 1 , wherein the quantum device is disposed on a first side of the substrate, and the at least one heater element is disposed on a second side of the substrate and aligned to the superconducting tunnel junction device on the first side the substrate.

11 . The device of claim 1 , wherein:
the at least one heater element comprises an inductive pickup coil and a resistive element connected to the inductive pickup coil; and the at least one heater element is disposed within a patterned void of a metallization feature on a surface of the substrate.

12 . The device of claim 1 , wherein the quantum device comprises a quantum bit, and the superconducting tunnel junction device is a Josephson junction of the quantum bit.

13 . The device of claim 1 , further comprising a wiring layer which comprises wiring that is electrically connected to the at least one heater element and configured to drive the at least one heater element with an external current applied on the wiring connected to the at least one heater element.

14 . A device, comprising:
a substrate; a plurality of quantum bits disposed on the substrate, each quantum bit comprising a Josephson junction; and a plurality of heater elements disposed on the substrate; wherein each heater element is disposed in proximity to a respective quantum bit of the plurality of quantum bits, and configured to generate heat through resistive heating in response to a current applied to the heater element, to heat a region of the substrate on which the Josephson junction of the respective quantum bit is disposed to thermally anneal the Josephson junction of the respective quantum bit.

15 . The device of claim 14 , wherein:
at least one heater element comprises at least one contact pad and a resistive element connected to the at least one contact pad; and the at least one heater element is disposed within a patterned void of a metallization feature on a surface of the substrate.

16 . The device of claim 15 , wherein the metallization feature comprises superconducting capacitor pad of a respective quantum bit.

17 . The device of claim 15 , wherein the metallization feature comprises a ground plane disposed on a surface of the substrate.

18 . The device of claim 15 , wherein the resistive element is serially connected to and between the at least one contact pad and the metallization feature.

19 . The device of claim 15 wherein:
the at least one contact pad comprises a first contact pad and a second contact pad; and
the resistive element is serially connected to and between the first contact pad and the second contact pad.

20 . The device of claim 15 , wherein the resistive element comprises one of a patterned metal trace and a doped region of the substrate.

21 . A method, comprising:
contacting electrical probes to a heater element disposed on a substrate; and applying a controlled current to the heater element through the electrical probes to cause the heater element to heat a portion of the substrate through resistive heating and thermally anneal a Josephson junction of a quantum bit, which is disposed in contact with the heated portion of the substrate.

22 . The method of claim 21 , wherein the controlled current comprises one of a direct current (DC) current pulse and alternating current (AC) current pulse.

23 . A method, comprising:
measuring a resistance of a Josephson junction of a quantum bit that is disposed on a substrate; and applying a controlled current to a heater element, which is disposed on the substrate in proximity to the Josephson junction of the quantum bit, to cause the heater element to generate heat through resistive heating and thereby heat a region of the substrate on which the Josephson junction is disposed to shift a resistance of the Josephson junction from the measured resistance to a target resistance.

24 . The method of claim 23 , wherein applying the current to the heater element comprises:
determining a difference between the measured resistance of the Josephson junction and the target resistance of the Josephson junction; and utilizing calibration data to determine parameters for configuring the controlled current based at least in part on the determined difference between the measured resistance and the target resistance of the Josephson junction.

25 . A system, comprising:
a prober apparatus; and a control system operatively coupled to the prober apparatus; wherein the control system is configured to control the prober apparatus to perform a tuning process to tune a transition frequency of at least one quantum bit of a quantum bit array on a quantum chip, wherein in performing the tuning process, the control system is configured to utilize the prober apparatus to:
measure a resistance of a Josephson junction of the at least one quantum bit;
apply a controlled current to an on-chip heater element, which is disposed in proximity to the Josephson junction of the at least one quantum bit, to cause the on-chip heater element to generate heat through resistive heating and thereby heat a region of the quantum chip on which the Josephson junction is disposed to shift a resistance of the Josephson junction from the measured resistance to a target resistance.

Assignees

• IBM

Inventors

• Hertzberg Jared Barney
• Sandberg Martin O
• Zhang Eric
• Orcutt Jason S

Classifications

• H10N60/12 Primary

  Josephson-effect devices · CPC title

• H05B1/0233

  for semiconductors manufacturing · CPC title

• H01P7/086

  Coplanar waveguide resonators (H01P7/088 takes precedence) · CPC title

• G01R27/08

  Measuring resistance by measuring both voltage and current · CPC title

• H10N60/805 Primary

  for Josephson-effect devices · CPC title