System, Device, and Method for Correcting a Duty Cycle

Patent metadata

Field	Value
Publication number	US-2026031803-A1
Application number	US-202418782073-A
Country	US
Kind code	A1
Filing date	Jul 24, 2024
Priority date	Jul 24, 2024
Publication date	Jan 29, 2026
Grant date	—

Abstract

A device includes a clock signal generator and a transmitter circuit. The clock signal generator receives a first input clock signal, generates an output clock signal, and includes a phase generator and a duty cycle corrector. The phase generator generates a plurality of second input clock signals from the input clock signal. The duty cycle corrector adjusts a duty cycle of the second input clock signal with reference to a control signal, generates a single-ended input signal and complementary output signals from the single-ended input signal, compares the complementary output signals, and generates a result of comparison that serves as the control signal. The transmitter circuit receives an input data signal, processes the input data signal in response to the output clock signal, generates an output data signal, and transmits the output data signal.

First claim

What is claimed is:

1 . A device comprising:
a clock signal generator configured to receive a first input clock signal and to generate an output clock signal and including:
a phase generator configured to generate a plurality of second input clock signals from the first input clock signal, each second input clock signal having a distinct phase;
a duty cycle corrector including:
a duty cycle altering circuit configured to adjust a duty cycle of the second input clock signal with reference to a control signal and to generate a single-ended input signal;
a differential signal generator configured to generate complementary output signals from the single-ended input signal; and
a comparator configured to compare the complementary output signals and to generate a result of comparison that serves as the control signal; and

a transmitter circuit configured to receive an input data signal, to process the input data signal in response to the output clock signal, to generate an output data signal, and to transmit the output data signal.

2 . The device of claim 1 , wherein the differential signal generator includes:
a converting circuit configured to convert the single-ended input signal into differential output signals; and an isolating circuit connected to converting circuit and configured to generate the complementary output signals that are amplified versions of the differential output signals, respectively.

3 . The device of claim 2 , wherein the differential signal generator further includes a routing circuit connected between an input and an output of the converting circuit and configured to compensate a delay introduced by the converting circuit.

4 . The device of claim 2 , wherein the differential signal generator further includes a routing circuit connected between an input and an output of the isolating circuit and configured to compensate a delay introduced by the isolating circuit.

5 . The device of claim 2 , wherein:
the converting circuit includes a first inverter and a second inverter connected in series with the first inverter; and a transmission gate connected between an input and an output of the second inverter.

6 . The device of claim 2 , wherein the isolating circuit includes:
a first inverter; a second inverter connected between the converting circuit and the first inverter; a third inverter; a fourth inverter connected between the converting circuit and the third inverter; and cross-coupled inverters connected between an output of the second inverter and an output of the fourth inverter.

7 . The device of claim 1 , further comprising a filter circuit connected between the differential signal generator and the comparator.

8 . A device comprising:
a clock signal generator configured to receive a first input clock signal and to generate an output clock signal and including:
a phase generator configured to generate a plurality of second input clock signals from the input clock signal, each second input clock signal having a distinct phase;
a duty cycle corrector including:
a duty cycle altering circuit configured to adjust a duty cycle of the second input clock signal with reference to complementary control signals and to generate a single-ended input signal;
a differential signal generator configured to convert the single-ended input signal into complementary output signals;
a comparator configured to compare the complementary output signals and to generate a control signal that indicates a result of comparison;
a digital signal generator configured to generate a digital signal that represents the control signal; and
a complementary signal generator configured to generate the complementary control signals in response to the digital signal; and

a receiver circuit configured to receive a first output data signal, to process the first output data signal in response to the output clock signal, to generate a second output data signal, and to provide the second output data signal as an output.

9 . The device of claim 8 , wherein the differential signal generator includes:
a converting circuit configured to convert the single-ended input signal into differential output signals; and an isolating circuit connected to converting circuit and configured to generate the complementary output signals that are amplified versions of the differential output signals, respectively.

10 . The device of claim 9 , wherein the differential signal generator further includes a routing circuit connected between an input and an output of the converting circuit and configured to compensate a delay introduced by the converting circuit.

11 . The device of claim 9 , wherein the differential signal generator further includes a routing circuit connected between an input and an output of the isolating circuit and configured to compensate a delay introduced by the isolating circuit.

12 . The device of claim 9 , wherein:
the converting circuit includes a first inverter and a second inverter connected in series with the first inverter; and a transmission gate connected between an input and an output of the second inverter.

13 . The device of claim 9 , wherein the isolating circuit includes:
a first inverter; a second inverter connected between the converting circuit and the first inverter; a third inverter; a fourth inverter connected between the converting circuit and the third inverter; and cross-coupled inverters connected between an output of the second inverter and an output of the fourth inverter.

14 . The device of claim 8 , further comprising a frequency divider connected between the differential signal generator and at least one of the comparator and the digital signal generator.

15 . The device of claim 8 , further comprising a filter circuit connected between the differential signal generator and the comparator.

16 . A method for correcting a duty cycle of a signal, the method comprising:
receiving a first input signal; generating a second input clock signal associated with the first input signal; generating a single-ended input signal by adjusting a duty cycle of the second input clock signal with reference to a first control signal; converting the single-ended input signal into first complementary output signals; comparing the first complementary output signals; and generating the first control signal based on a result of comparison.

17 . The method of claim 16 , further comprising:
adjusting the duty cycle of the second input clock signal with further reference to a second control signal that is a complement of the first control signal; generating a digital signal that represents the result of comparison; and generating the first and second control signals in response to the digital signal.

18 . The method of claim 16 , further comprising:
converting the single-ended input signal into second complementary output signals; dividing a frequency of one of the second complementary output signals to generate a third input signal; and generating the result of comparison in response to the third input signal.

19 . The method of claim 16 , further comprising attenuating the first complementary output signals with frequencies above a predetermined cutoff frequency.

20 . The method of claim 16 , wherein converting the single-ended input signal into first complementary output signals includes:
transforming the single-ended input signal into differential output signals; and routing at least one of the single-ended input signal

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Wei Shuo
• Lai Sheng-Tsung
• Li Chang-Yi

Classifications

• H03K3/037 Primary

  Bistable circuits · CPC title

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title