Electrical interconnects for packages containing photonic integrated circuits

Patent metadata

Field	Value
Publication number	US-2026026412-A1
Application number	US-202519345880-A
Country	US
Kind code	A1
Filing date	Sep 30, 2025
Priority date	Dec 29, 2023
Publication date	Jan 22, 2026
Grant date	—

Abstract

A method includes: providing an active photonic component of a photonic integrated circuit (PIC); attaching two electrodes to the active photonic component of the PIC; providing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 μm; and electrically connecting the first landing pad to one of the two electrodes.

First claim

What is claimed is:

1 . A method comprising:
receiving a photonic integrated circuit (PIC) that comprises an active photonic component operable under an electrical signal, and two electrodes coupled to the active photonic component; installing a first landing pad on a front surface of the PIC, wherein, when viewed from a direction perpendicular to the front surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 μm; electrically connecting the first landing pad to one of the two electrodes coupled to the active photonic component; receiving an electric integrated circuit (EIC) having an electrical component configured to provide the electrical signal, and a second landing pad electrically connected to the electrical component; and flip-chip bonding the EIC to the front surface of the PIC, wherein the electrical component of the EIC and the active photonic component are spaced apart by 2 mm or less.

2 . The method of claim 1 , further comprising:
plating a hole in the first landing pad using at least one of: a nickel material, or a gold material.

3 . The method of claim 2 , wherein the first landing pad is shaped as a polygon, an oval, or a circle.

4 . The method of claim 3 , wherein the plated hole in the first landing pad is at a center of the polygon, the oval, or the circle.

5 . The method of claim 3 , wherein the plated hole in the first landing pad is away from a center of the polygon or the circle.

6 . The method of claim 1 , wherein the first landing pad has a lateral dimension of less than 50 μm.

7 . The method of claim 2 , further comprising:
mating a flip-chip bump embedded in the second landing pad of the EIC with the plated hole in the first landing pad of the PIC when flip-chip bonding the EIC to the PIC.

8 . The method of claim 7 , wherein the flip-chip bump has a lateral dimension of 30 μm or less.

9 . The method of claim 1 , further comprising:
routing bias traces to a back surface of the PIC to form an interdigital filter, wherein the back surface is opposite to the front surface.

10 . The method of claim 9 , further comprising:
coupling the other one of the two electrodes to the interdigital filter.

11 . The method of claim 9 , wherein the interdigital filter comprises at least one of: a metal-oxide-metal capacitor (MOMCAP), a metal-insulator-metal capacitor (MIMCAP).

12 . The method of claim 9 , wherein the active photonic component is: an electro-absorption modulator (EAM), a ring modulator, an interference-based modulator, or a photodiode.

13 . The method of claim 12 , further comprising: electrically connecting the first landing pad to a cathode of the EAM.

14 . The method of claim 12 , further comprising: electrically connecting an anode of the EAM to the interdigital filter.

15 . The method of claim 1 , wherein the distance is in a range from 5 μm to 8 μm.

16 . A method comprising:
receiving a photonic integrated circuit (PIC) having an active photonic component and two electrodes coupled thereto, one of the two electrodes being electrically connected to a first landing pad of the PIC; receiving an electric integrated circuit (EIC) having a second landing pad where a flip-chip bump is embedded; and mating a plated hole in the first landing pad with the flip-chip bump embedded in the second landing pad when flip-chip bonding the EIC to a surface of the PIC, wherein, when viewed from a direction perpendicular to the surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 μm.

17 . The method of claim 16 , wherein the active photonic component is: an electro-absorption modulator (EAM), a ring modulator, an interference-based modulator, or a photodiode.

18 . The method of claim 16 , wherein the distance is in a range from 5 μm and 8 μm.

19 . A method comprising:
receiving a photonic integrated circuit (PIC) having an active photonic component attached to two electrodes, one of the two electrodes being electrically connected to a first landing pad where a flip-chip bump is embedded; receiving an electric integrated circuit (EIC) having a second landing pad with a plated hole; and mating the plated hole in the second landing pad with the flip-chip bump embedded in the first landing pad when flip-chip bonding the EIC to a surface of the PIC, wherein, when viewed from a direction perpendicular to the surface of the PIC, a center of the active photonic component of the PIC is offset from a nearest edge of the first landing pad by about a distance less than 10 μm.

20 . The method of claim 19 , wherein the active photonic component is: an electro-absorption modulator (EAM), a ring modulator, an interference-based modulator, or a photodiode.

21 . The method of claim 19 , wherein the distance is in a range from 5 μm to 8 μm.

Assignees

• Celestial Ai Inc

Inventors

• Staffaroni Matteo
• Park Kevin
• Vats Saurabh
• Sahni Subal
• Ozguc Ismail Hakki

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title