Semiconductor device

Patent metadata

Field	Value
Publication number	US-2026026043-A1
Application number	US-202519010762-A
Country	US
Kind code	A1
Filing date	Jan 6, 2025
Priority date	Jul 17, 2024
Publication date	Jan 22, 2026
Grant date	—

Abstract

A semiconductor device includes a substrate, a dielectric wall structure extending in a first direction on the substrate, active regions extending in the first direction, a gate structure extending in a second direction on the substrate, intersecting the dielectric wall structure, a plurality of channel layers on the active regions and spaced apart from each other in a third direction surrounded by the gate structure, and source/drain regions on at least one side of the gate structure. The dielectric wall structure includes a lower dielectric wall extending in the first direction, and a first upper dielectric wall overlapping the gate structure in the second direction, on the lower dielectric wall. A first upper surface of the lower dielectric wall in contact with the first upper dielectric wall has a first width, and a lower surface of the first upper dielectric wall has a second width less than the first width.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a dielectric wall structure extending in a first direction on the substrate; active regions extending in the first direction on sides of the dielectric wall structure; a gate structure extending in a second direction perpendicular to the first direction on the substrate, intersecting the dielectric wall structure; a plurality of channel layers on the active regions and spaced apart from each other in a third direction perpendicular to the first direction and the second direction, wherein the plurality of channel layers are at least partially surrounded by the gate structure; and source/drain regions on at least one side of the gate structure, on the sides of the dielectric wall structure, wherein the source/drain regions are electrically connected to the plurality of channel layers, wherein the dielectric wall structure comprises a lower dielectric wall extending in the first direction, and a first upper dielectric wall on the lower dielectric wall, and wherein a first upper surface of the lower dielectric wall has a first width, and a lower surface of the first upper dielectric wall has a second width less than the first width.

2 . The semiconductor device of claim 1 , wherein the plurality of channel layers comprises a first channel layer, and
wherein the first upper surface of the lower dielectric wall is coplanar with or closer to the substrate than an upper surface of the first channel layer.

3 . The semiconductor device of claim 2 , wherein the plurality of channel layers further comprise a second channel layer below the first channel layer and a third channel layer below the second channel layer, and
wherein the first upper surface of the lower dielectric wall is further from the substrate than an upper surface of the third channel layer.

4 . The semiconductor device of claim 2 , wherein a distance in the third direction between the first upper surface of the lower dielectric wall and the upper surface of the first channel layer is 20 nm or less.

5 . The semiconductor device of claim 2 , wherein a distance in the second direction between the first upper surface of the lower dielectric wall and the first channel layer is 1 nm to 5 nm.

6 . The semiconductor device of claim 1 , wherein the gate structure comprises:
a gate electrode at least partially surrounding the plurality of channel layers; gate dielectric layers respectively between the gate electrode and the plurality of channel layers, between the gate electrode and the dielectric wall structure, and between the gate electrode and one of the plurality of active regions; and gate spacer layers on side surfaces of the gate electrode, wherein the gate spacer layers are on the plurality of channel layers, and wherein the first upper dielectric wall comprises a material same as that of the gate spacer layers.

7 . The semiconductor device of claim 1 , wherein the dielectric wall structure further comprises a lower cladding film extending in the first direction between the lower dielectric wall and the active regions and between the lower dielectric wall and the substrate,
wherein the lower cladding film comprises a material different from that of the lower dielectric wall.

8 . The semiconductor device of claim 1 , wherein the dielectric wall structure further comprises an upper cladding film between at least one of the plurality of channel layers and the lower dielectric wall.

9 . The semiconductor device of claim 1 , wherein the first upper dielectric wall comprises a plurality of dielectric layers.

10 . The semiconductor device of claim 1 , wherein the dielectric wall structure comprises a second upper dielectric wall on the lower dielectric wall and partially overlapping the source/drain regions in the second direction,, and
wherein a second upper surface of the lower dielectric wall in contact with the second upper dielectric wall is closer to the substrate than the first upper surface.

11 . The semiconductor device of claim 10 , wherein the first upper dielectric wall and the second upper dielectric wall comprise a material different from that of the lower dielectric wall.

12 . The semiconductor device of claim 10 , wherein an upper surface of the second upper dielectric wall is further from the substrate than an upper surface of the first upper dielectric wall.

13 . The semiconductor device of claim 10 , wherein the second upper surface of the lower dielectric wall has a third width, and
wherein a fourth width of a lower surface of the second upper dielectric wall is less than the third width.

14 . The semiconductor device of claim 1 , wherein the first width is 10 nm to 25 nm, and
wherein the second width is 5 nm to 15 nm.

15 . A semiconductor device comprising:
a substrate; a dielectric wall structure extending in a first direction on the substrate; a gate structure extending in a second direction perpendicular to the first direction on the substrate, intersecting the dielectric wall structure, the gate structure comprising gate electrodes separated from each other by the dielectric wall structure; and a plurality of channel layers spaced apart from each other in a third direction perpendicular to the first direction and the second direction, wherein the plurality of channel layers are on sides of the dielectric wall structure, and the plurality of channel layers are respectively at least partially surrounded by the gate electrodes, wherein, in a region in which the dielectric wall structure overlaps the gate electrodes in the second direction, a side surface of the dielectric wall structure has a step structure.

16 . The semiconductor device of claim 15 , wherein the step structure of the dielectric wall structure is closer to the substrate than upper surfaces of the gate electrodes.

17 . The semiconductor device of claim 16 , wherein the side surface of the dielectric wall structure is inclined to have a decreasing width toward the substrate, closer to the substrate than the step structure.

18 . A semiconductor device comprising:
a substrate comprising an active region extending in a first direction; a gate structure extending in a second direction perpendicular to the first direction on the substrate, intersecting the active region; a dielectric wall structure extending in the first direction, the dielectric wall structure extending into the gate structure; source/drain regions in regions in which the active region is recessed, on sides of the gate structure; and a contact plug partially recessed into an upper surface of the source/drain region, wherein the contact plug is electrically connected to the source/drain region, wherein the dielectric wall structure comprises a first upper dielectric wall overlapping the gate structure in the second direction, a second upper dielectric wall comprising a region overlapping the source/drain region in the second direction, and a lower dielectric wall extending in the first direction below the first upper dielectric wall and the second upper dielectric wall, and wherein the first upper dielectric wall comprises a material having a dielectric constant, lower than that of the lower dielectric wall.

19 . The semiconductor device of claim 18 , wherein the first upper dielectric wall and the second upper dielectric wall comprise a material different from that of the lower dielectric wall.

20 . The semiconductor device of claim 18 . wherein the first upper dielectric

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Wooseok
• Koo Jehyoung
• Seo Donghyun

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10D30/506

  having different thicknesses, sizes or shapes · CPC title

• H10D30/0194

  the stacked channels having different properties · CPC title