Chaos system for failure predictions in computer architectures

Patent metadata

Field	Value
Publication number	US-2026023665-A1
Application number	US-202519269614-A
Country	US
Kind code	A1
Filing date	Jul 15, 2025
Priority date	Jul 22, 2024
Publication date	Jan 22, 2026
Grant date	—

Abstract

Aspects discussed herein may relate to methods and techniques for using a multi-step approach to automatically analyze the computer architecture using an iterative process to inject error conditions. After determining an ordered graph indicating possible failure points, the system may then inject one or more error conditions (e.g., increased latency) to determine possible effects and/or points of failure. As a result of this analysis, the system may modify analysis regarding possible error points and/or take remedial actions to avoid failure.

First claim

What is claimed is:

1 . A method comprising:
receiving, based on a mapping of one or more components in a computer architecture, an ordered graph indicating one or more relationships between the one or more components, wherein the ordered graph comprises mapped metadata; determining, by a machine learning model trained to perform structural analysis on the ordered graph, one or more failure points associated with the one or more components; iteratively injecting one or more error conditions into the one or more components, wherein the one or more error conditions comprise increased latency in communications between the one or more components; detecting, based on the iteratively injecting the one or more error conditions, one or more downstream effects of the one or more error conditions, wherein the one or more downstream effects comprise increased latency in communications between one or more other components; revising, by the machine learning model and based on the one or more downstream effects, the one or more failure points; and presenting, using a display, a visual representation of the one or more failure points.

2 . The method of claim 1 , wherein the one or more components comprise one or more of:
hardware components, or software components.

3 . The method of claim 1 , further comprising training the machine learning model based on historical component descriptions, wherein the historical component descriptions comprise:
domain-specific language associated with the computer architecture; and labeled images of diagram components.

4 . The method of claim 1 , further comprising training the machine learning model based on historical data associated with real-world failures.

5 . The method of claim 1 , wherein the one or more error conditions comprise one or more of:
downtime, bandwidth restrictions, error codes, judder, or excess traffic.

6 . The method of claim 1 , wherein the machine learning model comprises a Bayesian network model.

7 . The method of claim 1 , further comprising:
determining, based on the one or more failure points, one or more remedial actions for the computer architecture; and performing, based on detecting a failure of a subset of the one or more components, the one or more remedial actions.

8 . A computing device comprising:
one or more processors; and memory storing instructions that, when executed by the one or more processors, cause the computing device to perform: receive, based on a mapping of a first set of one or more components in a computer architecture, an ordered graph indicating one or more relationships between the first set of one or more components; determine, by a machine learning model trained to perform structural analysis on the ordered graph, one or more failure points associated with the first set of one or more components; iteratively inject one or more error conditions into the first set of one or more components, wherein the one or more error conditions comprise increased latency in communications between the one or more components; detect, based on the iteratively injecting the one or more error conditions, one or more downstream effects of the one or more error conditions, wherein the one or more downstream effects comprise increased latency in communications between a second set of one or more components different from the first set of one or more components; and revise, by the machine learning model and based on the one or more downstream effects, the one or more failure points.

9 . The computing device of claim 8 , wherein the first set of one or more components comprise one or more of:
hardware components, or software components.

10 . The computing device of claim 8 , wherein the machine learning model is trained based on:
domain-specific language associated with the computer architecture; and labeled images of diagram components.

11 . The computing device of claim 8 , wherein the machine learning model is trained based on historical data associated with real-world failures.

12 . The computing device of claim 8 , wherein the one or more error conditions comprise one or more of:
downtime, bandwidth restrictions, error codes, judder, or excess traffic.

13 . The computing device of claim 8 , wherein the machine learning model comprises a Bayesian network model.

14 . The computing device of claim 8 , instructions, when executed by the one or more processors, further cause the computing device to:
determine, based on the one or more failure points, one or more remedial actions for the computer architecture; and perform, based on detecting a failure of a subset of the first set of one or more components, the one or more remedial actions.

15 . A non-transitory computer-readable medium storing computer instructions that, when executed by one or more processors, cause performance of actions comprising:
receiving, based on a mapping of one or more components in a computer architecture, an ordered graph indicating one or more relationships between the one or more components, wherein the ordered graph comprises mapped metadata; determining, by a machine learning model trained to perform structural analysis on the ordered graph, one or more failure points associated with the one or more components;
iteratively injecting one or more error conditions into the one or more components;
detecting, based on the iteratively injecting the one or more error conditions, one or more downstream effects of the one or more error conditions;
revising, by the machine learning model and based on the one or more downstream effects, the one or more failure points;
determining, based on the one or more failure points, one or more remedial actions for the computer architecture; and
performing, based on detecting a failure of a subset of the one or more components, the one or more remedial actions.

16 . The non-transitory computer-readable medium storing computer instructions of claim 15 , wherein the one or more components comprise one or more of:
hardware components, or software components.

17 . The non-transitory computer-readable medium storing computer instructions of claim 15 , when executed by the one or more processors, further cause performance of actions comprising:
training the machine learning model based on one or more of:
domain-specific language associated with the computer architecture,
labeled images of diagram components, or
historical data associated with real-world failures.

18 . The non-transitory computer-readable medium storing computer instructions of claim 15 , wherein the one or more error conditions comprise one or more of:
latency, downtime, bandwidth restrictions, error codes, judder, or excess traffic.

19 . The non-transitory computer-readable medium storing computer instructions of claim 15 , wherein the machine learning model comprises a Bayesian network model.

20 . The non-transitory computer-readable medium storing computer instructions of claim 15 , when executed by the one or more processors, further cause performance of actions comprising:
presenting, using a display, a user interface indicating the one or more failure points.

Assignees

• Capital One Services Llc

Inventors

• Gaynor Kevin
• Ciramdas Vamshi Krishna
• Chikkaveerappa Satish
• Russo Matthew Attilio

Classifications

• G06F11/079

  Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36) · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/2273 Primary

  Test methods · CPC title

• G06F11/004

  Error avoidance (G06F11/07 and subgroups take precedence) · CPC title

• G06F11/327

  Alarm or error message display · CPC title