Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2026020240-A1
Application number	US-202519334579-A
Country	US
Kind code	A1
Filing date	Sep 19, 2025
Priority date	Jan 3, 2022
Publication date	Jan 15, 2026
Grant date	—

Abstract

The present discloses relates to a semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device includes a stacked structure including insulating layers and conductive layers stacked alternately with each other, a channel structure passing through at least a portion of the stacked structure, and a memory layer interposed between the conductive layers and the channel structure, wherein the memory layer includes a floating gate arranged between the conductive layers and the channel structure.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a stacked structure including insulating layers and conductive layers stacked alternately with each other; a channel structure passing through at least a portion of the stacked structure; and a memory layer interposed between the conductive layers and the channel structure, wherein the memory layer includes a charge trap layer and a floating gate arranged sequentially between the conductive layers and the channel structure. and, wherein an upper surface of the floating gate is directly contact in an one of the insulating layer.

2 . The semiconductor device of claim 1 , wherein the insulating layers protrude in a direction toward the channel structure more than the conductive layers, and
wherein the charge trap layer and the floating gate are arranged between the insulating layers.

3 . The semiconductor device of claim 2 , wherein the memory layer includes a blocking insulating layer, the charge trap layer, and the floating gate, arranged sequentially between the conductive layers and the channel structure,
wherein the blocking insulating layer is arranged between the insulating layers and wherein the blocking insulating layer is arranged at an interface between the charge trap layer and the insulating layers and an interface between the charge trap layer and the conductive layers.

4 . The semiconductor device of claim 2 , wherein the memory layer includes the charge trap layer, the floating gate, and a tunnel isolation layer arranged sequentially between the conductive layers and the channel structure, and
wherein the tunnel isolation layer surrounds a sidewall of the channel structure.

5 . The semiconductor device of claim 1 , wherein the charge trap layer disposed outside the floating gate around the channel structure.

6 . The semiconductor device of claim 1 , wherein an upper surface of the charge trap layer is directly contact in the one of the insulating layers.

7 . The semiconductor device of claim 1 , wherein the memory layer includes a blocking insulating layer, the charge trap layer, and the floating gate, arranged sequentially between the conductive layers and the channel structure, and
wherein the floating gate includes polysilicon and the blocking insulating layer includes a high-k material.

8 . The semiconductor device of claim 7 , wherein the blocking insulating layer is disposed outside the charge trapping layer around the channel structure.

9 . The semiconductor device of claim 7 , wherein an upper surface of the blocking insulating layer is directly contact in the one of the insulating layers.

10 . The semiconductor device of claim 1 , wherein the charge trap layer includes at least one of a chalcogenide compound and a metal compound.

11 . A semiconductor device, comprising:
a stacked structure including insulating layers and conductive layers stacked alternately with each other; a channel structure passing through at least a portion of the stacked structure; and a memory layer interposed between the conductive layers and the channel structure, wherein the memory layer includes charge trap layers and floating gates disposed at a same level as the conductive layers of the stacked structure, and, wherein the floating gates are separated from each other along a stacking direction of the insulating layers and the conductive layers.

12 . The semiconductor device of claim 11 , wherein one of the charge trap layers and one of the floating gates are arranged sequentially between the conductive layers and the channel structure.

13 . The semiconductor device of claim 11 , wherein the insulating layers protrude in a direction toward the channel structure more than the conductive layers, and
wherein one of the charge trap layers and one of the floating gates are arranged between the insulating layers.

14 . The semiconductor device of claim 13 , wherein the memory layer includes a blocking insulating layer, one of the charge trap layers, and one of the floating gates, arranged sequentially between the conductive layers and the channel structure,
wherein the blocking insulating layer is arranged between the insulating layers and wherein the blocking insulating layer is arranged at an interface between the one of the charge trap layers and the insulating layers and an interface between the one of the charge trap layers and the conductive layers.

15 . The semiconductor device of claim 13 , wherein the memory layer includes the one of the charge trap layers, the one of the floating gates, and a tunnel isolation layer arranged sequentially between the conductive layers and the channel structure, and
wherein the tunnel isolation layer surrounds a sidewall of the channel structure.

16 . The semiconductor device of claim 11 , wherein the one of the charge trap layers disposed outside the one of the floating gates around the channel structure.

17 . The semiconductor device of claim 11 , wherein an upper surface of the one of the charge trap layers is directly contact in the one of the insulating layers.

18 . The semiconductor device of claim 11 , wherein the memory layer includes a blocking insulating layer, the one of the charge trap layers, and the one of the floating gates, arranged sequentially between the conductive layers and the channel structure, and
wherein the one of the floating gates includes polysilicon and the blocking insulating layer includes a high-k material.

19 . The semiconductor device of claim 18 , wherein the blocking insulating layer is disposed outside the charge trapping layer around the channel structure.

20 . The semiconductor device of claim 12 , wherein the one of the charge trap layers includes at least one of a chalcogenide compound and a metal compound.

Assignees

• Sk Hynix Inc

Inventors

• Han Jae Hyun

Classifications

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title